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온-저항 특성 향상을 위한 게이트 패드 구조에 관한 연구
강예환,유원영,김우택,박태수,정은식,양창헌,Kang, Ye-Hwan,Yoo, Won-Young,Kim, Woo-Taek,Park, Tae-Su,Jung, Eun-Sik,Yang, Chang Heon 한국전기전자재료학회 2015 전기전자재료학회논문지 Vol.28 No.4
Power MOSFETs (metal oxide semiconductor field effect transistor) operate as energy control semiconductor switches. In order to reduce energy loss of the device during switch-on state, it is essential to increase its conductance. In this study we have investigated a structure to reduce the on-resistance characteristics of the MOSFET. We have a proposed MOSFET structure of active cells region buried under the gate pad. The measurement are carried out with a EDS to analyze electrical characteristics, and the proposed MOSFET are compared with the conventional MOSFET. The result of proposed MOSFET was 1.68[${\Omega}$], showing 10% improvement compared to the conventional MOSFET at 700[V].
3.3kV SiC MOSFET 설계 및 제작을 위한 JFET 및 FLR 최적화 연구
구상모,강예환,이현우 한국반도체디스플레이기술학회 2023 반도체디스플레이기술학회지 Vol.22 No.3
The potential performance benefits of Silicon Carbide(SiC) MOSFETs in high power, high frequency power switching applications have been well established over the past 20 years. In the past few years, SiC MOSFET offerings have been announced by suppliers as die, discrete, module and system level products. In high-voltage SiC vertical devices, major design concerns is the edge termination and cell pitch design Field Limiting Rings(FLR) based structures are commonly used in the edge termination approaches. This study presents a comprehensive analysis of the impact of variation of FLR and JFET region on the performance of a 3.3 kV SiC MOSFET during. The improvement in MOSFET reverse bias by optimizing the field ring design and its influence on the nominal operating performance is evaluated. And, manufacturability of the optimization of the JFET region of the SiC MOSFET was also examined by investigating full-map electrical characteristics.
500 V 급 Planar Power MOSFET의 P 베이스 농도 변화에 따른 설계 및 특성 향상에 관한 연구
김권제,강예환,권영수,Kim, Gwon Je,Kang, Ye Hwan,Kwon, Young-Soo 한국전기전자재료학회 2013 전기전자재료학회논문지 Vol.26 No.4
Power MOSFETs(Metal Oxide Semiconductor Field Effect Transistor) operate as energy control semiconductor switches. In order to reduce energy loss of the device during switch-on state, it is essential to increase its conductance. We have experimental results and explanations on the doping profile dependence of the electrical behavior of the vertical MOSFET. The device is fabricated as $8.25{\mu}m$ cell pitch and $4.25{\mu}m$ gate width. The performances of device with various p base doping concentration are compared at Vth from 1.77 V to 4.13 V. Also the effect of the cell structure on the on-resistance and breakdown voltage of the device are analyzed. The simulation results suggest that the device optimized for various applications can be further optimized at power device.
"Si 증착 이후 형성된 게이트 산화막을 이용한 SiC MOSFET의 전기적 특성"
조영훈,강예환,박창준,김지현,이건희,구상모 한국전기전자학회 2024 전기전자학회논문지 Vol.28 No.1
"이번 연구에서 우리는 게이트 산화막을 형성하기 위해 Si을 증착한 후 산화시킨 SiC MOSFET의 전기적 특성을 연구했다. 고품질의 Si/SiO2 계면을 제작하기 위해 얇은 Si 층을 SiC epi 층 위에 약 20 nm을 증착한 후 산화하여 게이트 산화막을 약 55 nm로형성했다. SiC를 산화하여 게이트 산화막을 제작한 소자와 계면 트랩 밀도, 온저항, 전계-효과 이동도의 측면에서 비교했다. 위 소자는 향상된 계면 트랩 밀도 (~8.18 × 1011 eV-1cm-2), 전계-효과 이동도 (27.7 cm2/V·s), 온저항 (12.9 mΩ·cm2)을 달성하였다." "In this study, we investigated the electrical characteristics of SiC MOSFETs by depositing Si and oxidizing it to form the gate oxide layer. A thin Si layer was deposited approximately 20 nm thick on top of the SiC epi layer, followed by oxidation to form a gate oxide layer of around 55 nm. We compared devices with gate oxide layers produced by oxidizing SiC in terms of interface trap density, on-resistance, and field-effect mobility. The fabricated devices achieved improved interface trap density (~8.18 × 1011 eV-1cm-2), field-effect mobility (27.7 cm2/V·s), and on-resistance (12.9 mΩ·cm2 )."
8인치 Si Power MOSFET Field Ring 영역의 도핑농도 변화에 따른 전기적 특성 비교에 관한 연구
김권제,강예환,권영수,Kim, Gwon Je,Kang, Ye Hwan,Kwon, Young-Soo 한국전기전자재료학회 2013 전기전자재료학회논문지 Vol.26 No.4
Power Metal Oxide Semiconductor Field Effect Transistor's (MOSFETs) are well known for superior switching speed, and they require very little gate drive power because of the insulated gate. In these respects, power MOSFETs approach the characteristics of an "ideal switch". The main drawback is on-resistance RDS(on) and its strong positive temperature coefficient. While this process has been driven by market place competition with operating parameters determined by products, manufacturing technology innovations that have not necessarily followed such a consistent path have enabled it. This treatise briefly examines metal oxide semiconductor (MOS) device characteristics and elucidates important future issues which semiconductor technologists face as they attempt to continue the rate of progress to the identified terminus of the technology shrink path in about 2020. We could find at the electrical property as variation p base dose. Ultimately, its ON state voltage drop was enhanced also shrink chip size. To obtain an optimized parameter and design, we have simulated over 500 V Field ring using 8 Field rings. Field ring width was $3{\mu}m$ and P base dose was $1e15cm^2$. Also the numerical multiple $2.52cm^2$ was obtained which indicates the doping limit of the original device. We have simulated diffusion condition was split from $1,150^{\circ}C$ to $1,200^{\circ}C$. And then $1,150^{\circ}C$ diffusion time was best condition for break down voltage.
심관필,안병섭,강예환,홍영성,강이구,Sim, Gwan Pil,Ann, Byoung Sup,Kang, Ye Hwan,Hong, Young Sung,Kang, Ey Goo 한국전기전자재료학회 2013 전기전자재료학회논문지 Vol.26 No.3
Power MOSFET and Power IGBT is develop in power savings, high efficiency, small size, high reliability, fast switching, low noise. Power MOSFET can be used high-speed switching transistors devices. Power MOSFET is devices the voltage-driven approach switching devices are design to handle on large power, power supplies, converters. In this paper, design the 80V MOSFET Planar Gate type, and design the Trench Gate type for realization of low on-resistance. For both structures, by comparing and analyzing the results of the simulation and characterization.
N-이온주입이 4H-SiC SBDs의 깊은 준위 결함 및 소수캐리어 수명에 미치는 영향
신명철,이건희,강예환,오종민,신원호,구상모 한국전기전자학회 2023 전기전자학회논문지 Vol.27 No.4
본 연구에서는 4H-SiC Epi Surface에 Nitrogen implantation 공정이 깊은준위결함과 lifetime에 미치는 영향을 비교분석하였다. Deep Level Transient Spectroscopy (DLTS)와 Time Resolved Photoluminescence (TR-PL)을 사용하여 깊은준위결함과carrier lifetime을 측정하였다. As-grown SBD에서는 0.16 eV, 0.67 eV, 1.54 eV 에너지 준위와 implantation SBD의 경우0.15 eV 준위에서의 결함을 측정되었으며, 이는 nitrogen implantation으로 불순물이 titanium 및 carbon vacancy를 대체됨으로 lifetime killer로 알려진 Z1/2, EH6/7 준위 결함은 감소하였다. In this study, the impact of Nitrogen implantation process on deep-level defects and lifetime in 4H-SiC Epi surfaceswas comparatively analyzed. Deep Level Transient Spectroscopy (DLTS) and Time Resolved Photoluminescence (TR-PL)were employed to measure deep-level defects and carrier lifetime. As-grown Schottky Barrier Diodes (SBDs)exhibited energy levels at 0.16 eV, 0.67 eV, and 1.54 eV, while for implantation SBD, defects at 0.15 eV wereobserved. This indicates a reduction in defects associated with energy levels Z1/2 and EH6/7, known as lifetimekillers, as impurities from nitrogen implantation replace titanium and carbon vacancies.
4H-SiC 기반으로 제작된 MPS Diode의 Schottky 영역 비율에 따른 전기적 특성 분석
이형진 ( Hyung-jin Lee ),강예환 ( Ye-hwan Kang ),정승우 ( Seung-woo Jung ),이건희 ( Geon-hee Lee ),변동욱 ( Dong-wook Byun ),신명철 ( Myeong-choel Shin ),양창헌 ( Chang-heon Yang ),구상모 ( Sang-mo Koo ) 한국전기전자재료학회 2022 전기전자재료학회논문지 Vol.35 No.3
In this study, we measured and comparatively analyzed the characteristics of MPS (Merged Pin Schottky) diodes in 4H-SiC by changing the areal ratio between the Schottky and PN junction region. Increasing the temperature from 298 K to 473 K resulted in the threshold voltage shifting from 0.8 V to 0.5 V. A wider Schottky region indicates a lower on-resistance and a faster turn-on. The effective barrier height was smaller for a wider Schottky region. Additionally, the depletion layer became smaller under the influence of the reduced effective barrier height. The wider Schottky region resulted in the ideality factor being reduced from 1.37 to 1.01, which is closer to an ideal device. The leakage saturation current increased with the widening Schottky region, resulting in a 1.38 times to 2.09 times larger leakage current.
비냉각형 적외선 검출기의 마이크로 캔틸레버 휨 현상 개선 연구
이명환(Myung-Hwan Lee),강예환(Ye-Hwan Kang),정은식(Eun-Sik Jung),강태영(Tae-Young Kang),강이구(Ey-Goo Kang) 대한전기학회 2010 대한전기학회 학술대회 논문집 Vol.2010 No.7
본 논문은 마이크로 볼로미터 어레이 제작 공정 시 캔틸레버 휨 현상을 개선하기 위해 고온 공정을 저온 공정으로 대체하였으며, 또한 구조적인 개선을 위해 마이크로 볼로미터의 샌드위치 구조를 제안하고 제작하여 구조적 안정도와 특성을 분석하였다.