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- 주제어 : ARM7TDMI (검색결과 6 건)
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오민석,김재우,김영훈,남기훈,이광엽 대한전자공학회 2004 電子工學會論文誌-CI (Computer and Information) Vol.40 No.12
현재 ARM7 TDMI 마이크로프로세서는 소프트웨어 루틴들의 반복 알고리듬을 사용하여 정수 나눗셈 연산을 처리하고 있어 많은 명령어 수와 긴 수행 시간을 갖는다. 본 논문은 ARM7 TDMI 마이크로프로세서의 연산기능 중 구현되지 않은 정수 나눗셈 연산 기능을 제안하였다. 이를 위해 부호 없는 정수 나눗셈 명령어인 ‘UDIV’명령어와 부호 있는 정수 나눗셈 명령어인 ‘SDIV’ 명령어를 새로 정의하였으며, 명령어들의 수행하기 위해 ARM7 TDMI 마이크로프로세서의 데이터 패스에 나눗셈 알고리듬을 적용하였다. 적용한 나눗셈 알고리듬은 비복원 알고리듬이며, 기존의 데이터 패스를 최대한 이용하여 추가되는 하드웨어 유닛을 최대한 줄였다. 제안된 방법을 검증하기 위하여 HDL(Hardware Description Language)을 이용하여 RTL(Register Transfer Level)에서 설계하여 시뮬레이션 하였으며, 현재 ARM7 TDMI 마이크로프로세서의 정수 나눗셈 연산 처리 방법과 제안된 구조에서의 정수 나눗셈 연산 처리 방법을 수행 시간과 수행 명령어 수 측면에서 비교하였으며, 기존의 논문에서 제안한 정수 나눗셈기와 수행 시간과 추가되는 하드웨어 면적을 비교하였다. The ARM7 TDMI microprocessor employ a software routine iteration method in order to handle integer division operation, but this method has long execution time and many execution instruction. In this paper, we proposed ARM7 TDMI microprocessor with integer division instruction. To make this, we additionally defined UDIV instruction for unsigned integer division operation and SDIV instruction for signed integer division operation, and proposed ARM7 TDMI microprocessor data Path to apply division algorithm. Applied division algorithm is nonrestoring division algorithm and additive hardware is reduced using existent ARM data path. To verify the proposed method, we designed proposed method on RTL level using HDL, and conducted logic simulation. we estimated the number of execution cycles and the number of execution instructions as compared proposed method with a software routine iteration method, and compared with other published integer divider from the number of execution cycles and hardware size.
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A Design of Fuzzy PID Controller Based on ARM7TDMI for Coupled-Tanks Process
Ronnapop Jaisue,Jutarut Chaoraingern,Vittaya Tipsuwanporn,Arjin Numsomran,Phayupp Pholkeaw 제어로봇시스템학회 2012 제어로봇시스템학회 국제학술대회 논문집 Vol.2012 No.10
This paper presents the design of Fuzzy PID controller based on ARM7TDMI for coupled-tanks process. The research is developed from previous studying of modified quadrupled-tanks process in the case of non-interacting second order process. The PID controller is designed by root locus technique, then it is improved a performance by combining with Fuzzy inference system for desired output response specification. Furthermore, PID Fuzzy inference system has been approximated into lookup table scheme for properly running on ARM7 embedded system. With the proposed method, the efficiency control algorithm can be performed on ARM7 platform that has a good performance and affordable costs. The experimental results have been shown that the design of Fuzzy PID embedded controller can achieve the performance specification requirement in level control.
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SoC(System on Chip) 기반의 임베디드 실험 키트 및 응응 프로그램의 개발
이재만,이연옥,이승호 한밭대학교 2006 한밭대학교 논문집 Vol.23 No.-
In this thesis, and embedded system is developed. The developed embedded system is a embedded experim with A7S SoC device integrated ARM7TDMI microprocessor with FPGA. An embedded linux is ported on the embedded system Based on the embedded system ported embedded OS, I study a practical application skill using SoC. Some interfaces for controlling some peripheral devices using SoC are implemented in developed embedded system. A digital logic is also implemented in SoC. It is proved that the embedded system using SoC gets a convenience of system design and some advantages of performance compared with the embedded system using microprocessor as a result.
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Hardware-Software Implementation of MPEG-4 Video Codec
김성민,서기범,엄낙웅,김경숙,Ju-HyunPark,Seong-MoPark,Bon-TaeKoo,Kyoung-SeonShin,Ig-KyunKim 한국전자통신연구원 2003 ETRI Journal Vol.25 No.6
This paper presents an MPEG-4 video codec, called MoVa, for video coding applications that adopts 3G-324M. We designed MoVa to be optimal by embedding a costeffective ARM7TDMI core and partitioning it into hardwired blocks and firmware blocks to provide a reasonable tradeoff between computational requirements, power consumption, and programmability. Typical hardwired blocks are motion estimation and motion compensation, discrete cosine transform and quantization, and variable length coding and decoding, while intra refresh, rate control, error resilience, error concealment, etc. are implemented by software. MoVa has a pipeline structure and its operation is performed in four stages at encoding and in three stages at decoding. It meets the requirements of MPEG-4 SP@L2 and can perform either 30 frames/s (fps) of QCIF or SQCIF, or 7.5 fps (in codec mode) to 15 fps (in encode/decode mode) of CIF at a maximum clock rate of 27 MHz for 128 kbps or 144 kbps. MoVa can be applied to many video systems requiring a high bit rate and various video formats, such as videophone, videoconferencing, surveillance, news, and entertainment.
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Wireless Modem SoC Implementation for Industrial Applications
Sun-Hee Kim,Do-Hoon Kim,Jin-Woong Cho 대한전자공학회 2009 ITC-CSCC :International Technical Conference on Ci Vol.2009 No.7
The Koinonia is an ISO/IEC JTC1 international standard that describes PHY/MAC functions for ad hoc wireless networks to support QoS in an industrial work environment. In this paper, we have designed FPGA of Koinonia PHY functions and implemented SoC with Koinonia PHY/MAC functions and several peripheral devices. This 6Mbps modem SoC includes ARM7TDMI, 64Kbyte SRAM and ADC/DAC for flexible applications. The modem SoC can also support various communication interfaces such as 16bit PCMCIA, USB, and 16C550 compatible UART. The Koinonia SoC chip can be used for consumer electronics applications such as A/V transmission, and replacement of conventional WLAN/WPAN in industrial applications.
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