Near-field clutter artifact reduction algorithm based on wavelet thresholding method in echocardiography using 3D printed cardiac phantom

Kim Minkyoung,Han Dong-Kyoon,Lee Youngjin 한국물리학회 2022 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.81 No.5

One of the typical sources of noise of echocardiography, near-feld clutter (NFC), is an artifact in the near feld and causes diagnostic errors with decreased accuracy. The purpose of this study is to apply an algorithm based on the wavelet thresholding method to remove only the NFC area, without afecting the essential regions for accurate diagnosis. Ultrasound images including NFC were obtained using a self-manufactured left ventricle (LV) phantom, after which comparative evaluation was performed after applying a wavelet thresholding method-based algorithm. When the algorithm based on the wavelet thresholding method was applied to the NFC image, the root mean square error (RMSE) value decreased by 71.38%, from 35.54 to 10.17. The correlation coefcient (CC) value increased by 12.64%, from 0.87 to 0.98, and the mean structural similarity (MSSIM) value increased by 23.68%, from 0.76 to 0.94. Finally, the universal quality index (UQI) value increased by 17.28%, from 0.81 to 0.95. In conclusion, the algorithm based on the wavelet thresholding method proved efective for removing signifcant NFCs, which afect image diagnosis in echocardiography. Furthermore, when this algorithm is used in cardiac ultrasound machines, it is expected to improve the accuracy of diagnosis by removing NFC.

Design of a 22-nm FinFET-Based SRAM With Read Buffer for Near-Threshold Voltage Operation

Juhyun Park,Younghwi Yang,Hanwool Jeong,Seung Chul Song,Wang, Joseph,Yeap, Geoffrey,Seong-Ook Jung Institute of Electrical and Electronics Engineers 2015 IEEE transactions on electron devices Vol. No.

<P>A near-threshold voltage (V<SUB>th</SUB>) operation circuit is important for both energy- and performance-constrained applications. The conventional 6-T SRAM bit-cell designed for super-V<SUB>th</SUB> operation cannot achieve the target SRAM bit-cell margins such as the hold stability, read stability, and write ability margins in the near-V<SUB>th</SUB> region. The recently proposed SRAM bit-cells with read buffer suffer from the problems of low read 0 sensing margin and large read 1 sensing time in the near-V<SUB>th</SUB> region. This paper proposes a read buffer with adjusted the number of fins or V<SUB>th</SUB> to resolve the problems in the near-V<SUB>th</SUB> region. This paper also proposes a design method for pull-up, pull-down, and pass-gate transistors to achieve the target hold stability and presents an effective write assist circuit to achieve the target write ability in the near-V<SUB>th</SUB> region.</P>

Voltage and Frequency Tuning Methodology for Near-Threshold Manycore Computing using Critical Path Delay Variation

Li, Chang-Lin,Kim, Hyun Joong,Heo, Seo Weon,Han, Tae Hee The Institute of Electronics and Information Engin 2015 Journal of semiconductor technology and science Vol.15 No.6

Near-threshold computing (NTC) is now regarded as a promising candidate for innovative power reduction, which cannot be achieved with conventional super-threshold computing (STC). However, performance degradation and vulnerability to process variation in the NTC regime are the primary concerns. In this paper, we propose a voltage- and frequency-tuning methodology for mitigating the process-variation-induced problems in NTC-based manycore architectures. To implement the proposed methodology, we build up multiple-voltage multiple-frequency (MVMF) islands and apply a voltage-frequency tuning algorithm based on the critical-path monitoring technique to reduce the effects of process variation and maximize energy efficiency in the post-silicon stage. Experimental results show that the proposed methodology reduces overall power consumption by 8.2-20.0%, compared to existing methods in variation-sensitive NTC environments.

Near-threshold photoproduction of φ mesons from deuterium

CLAS Collaboration,Qian, X.,Chen, W.,Gao, H.,Hicks, K.,Kramer, K.,Laget, J.M.,Mibe, T.,Qiang, Y.,Stepanyan, S.,Tedeschi, D.J.,Xu, W.,Adhikari, K.P.,Amaryan, M.,Anghinolfi, M.,Ball, J.,Battaglieri, M. North-Holland Pub. Co 2011 Physics letters: B Vol.696 No.4

We report the first, kinematically-complete measurement of the differential cross section of φ-meson photoproduction from deuterium near the production threshold for a proton using the CLAS detector and a tagged-photon beam in Hall B at Jefferson Lab. The measurement was carried out by a triple coincidence detection of a proton, K<SUP>+</SUP> and K<SUP>-</SUP> near the theoretical production threshold of 1.57 GeV. The extracted differential cross sections dσdt for the initial photon energy range of 1.65-1.75 GeV are consistent with predictions based on a quasifree mechanism. Our finding is different from recent LEPS results on φ-meson photoproduction from deuterium in a similar incident photon energy range, but in a different momentum transfer region.

Voltage and Frequency Tuning Methodology for Near- Threshold Manycore Computing using Critical Path Delay Variation

Chang-Lin Li,Hyun Joong Kim,Seo Weon Heo,Tae Hee Han 대한전자공학회 2015 Journal of semiconductor technology and science Vol.15 No.6

Near-threshold computing (NTC) is now regarded as a promising candidate for innovative power reduction, which cannot be achieved with conventional super-threshold computing (STC). However, performance degradation and vulnerability to process variation in the NTC regime are the primary concerns. In this paper, we propose a voltage- and frequency-tuning methodology for mitigating the process-variation-induced problems in NTC-based manycore architectures. To implement the proposed methodology, we build up multiplevoltage multiple-frequency (MVMF) islands and apply a voltage-frequency tuning algorithm based on the critical-path monitoring technique to reduce the effects of process variation and maximize energy efficiency in the post-silicon stage. Experimental results show that the proposed methodology reduces overall power consumption by 8.2–20.0%, compared to existing methods in variation-sensitive NTC environments.

Single-Ended 9T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Read Performance in 22-nm FinFET Technology

Younghwi Yang,Juhyun Park,Seung Chul Song,Wang, Joseph,Yeap, Geoffrey,Seong-Ook Jung IEEE 2015 IEEE transactions on very large scale integration Vol.23 No.11

<P>Although near-threshold (Vth) operation is an attractive method for energy and performance-constrained applications, it suffers from problems in terms of circuit stability, particularly, for static random access memory (SRAM) cells. This brief proposes a near-Vth 9T SRAM cell implemented in a 22-nm FinFET technology. The read buffer of the proposed cell ensures read stability by decoupling the stored node from the read bit-line and improves read performance using a one-transistor read path. Energy and standby power are reduced by eliminating the sub-Vth leakage current in the read buffer. For accurate sensing yield estimation, a new yield-estimation method is also proposed, which considers the dynamic trip voltage. The proposed SRAM cell can achieve a minimum operating voltage of 0.3 V.</P>

저전력 및 저전압 동작을 위한 단락 전류 없는 위상 압축 플립플롭

강경훈,정완영 대한전자공학회 2023 전자공학회논문지 Vol.60 No.11

기존의 위상 압축 플립플롭(TCFF)은 내부 노드의 데이터 전환을 줄이고 트랜지스터 수를 최소화하여 높은 에너지 효율을 달성하지만, NTV(Near Threshold Voltage) 수준에서 동작할 경우 기능 장애로 이어질 수 있는 동작 실패 case가 존재한다. 이러한 문제를 해결하여 제시된 플립플롭(SCTCFF)은 전력 손실 없이 0.3V까지 동작할 수 있습니다. 65nm CMOS 공정을 사용하여 FF의 테스트 회로에서 SCTCFF는 1V, 10%/20%의 activitiy ratio에서 TGFF에 비해 44.4%/39.0%의 전력을 절약하는 것으로 나타났습니다. The conventional topologically-compressed flip-flop (TCFF) achieves high energy efficiency by reducing the data activity ratio of internal nodes and minimizing transistor counts. However, it suffers from a race condition that it can lead to functional failure when operating at near-threshold voltage (NTV) levels. By resolving this issue, the presented flip-flop (SCTCFF) can operate down to 0.3V without power loss. In a test circuit of FFs utilizing 65nm CMOS process shows that SCTCFF saves 44.4% / 39.0% power compared to TGFF with 10% / 20% activity at 1V.

NTV 영역에서 안정적으로 동작 가능한 저전력 16-트랜지스터 단상 클럭 Flip-Flop

석준하,김혜선,김소영 대한전자공학회 2024 전자공학회논문지 Vol.61 No.2

본 논문은 Near-threshold voltage (NTV) 영역에서 안정적으로 동작 가능한 새로운 저전력 16-transistor single-phase clock (16TSPC) flip-flop (FF) 구조를 제안한다. 16TSPC는 contention-free과 fully static operation이 가능하게 설계하였다. 따라서, FF의 동적 (dynamic) 전력 소비가 감소되고, NTV 영역에서 공정 변동에 의한 동작 오류 없이 안정적으로 동작하도록 하였다. 광범위한 동작 전압 (1V∼0.3V)에서 동작이 가능하도록 하였다. 그리고, NTV영역에서 16TSPC의 성능 및 신뢰성을 확인하기 위해 28nm process design kit (PDK)를 적용하여 시뮬레이션을 진행하였다. 저전력 동작 전압 0.4V에서 16TSPC의 성능을 기존의 FF 구조 대비 전력소모, CLK-to-Q delay, power delay product (PDP) 및 레이아웃 면적을 비교하였다. 또한 16TSPC 구조의 신뢰성을 평가하기 위해, 몬테-카를로 시뮬레이션을 진행하여 기존 FF들 대비 안정적 동작이 가능함을 증명하였다. In this paper, we propose a new low-power 16-transistor single-phase clock (16TSPC) flip-flop (FF) that can operate reliably in the near-threshold voltage (NTV) region. The 16TSPC is designed to completely eliminate contention and enable fully static operation. Therefore, the dynamic power consumption of the FF is reduced, and it can operate stably in the NTV region without operation errors caused by process variations. In addition, since it operates stably without operation errors, it is possible to operate over a wide range of operating voltages (1V to 0.3V). Then, to verify the performance and reliability of the 16TSPC in the NTV region, simulations were conducted using a 28nm process design kit (PDK). We compared the power consumption, CLK-to-Q delay, power delay product (PDP) and layout area of the proposed 16TSPC with respect to other designs. Also to test the reliability, we performed the Monte-Carlo simulations and compared the results with those of conventional designs.

TMCP 고장력강 용접 부의 하한계 피로균열진전 특성평가

이택순(Taik-Soon Lee),오대석(Dae-Sek Oh),이휘원(Hwi-Won Lee) 한국해양공학회 1997 韓國海洋工學會誌 Vol.11 No.3

Recently developed TMCP steels, which were manufactured by controlled rolling followed by accelerated cooling process, were examined to study their characteristics and weldability. Accelerated cooling type TMCP steel’s hardness test result exhibited high value on weld zone. On the contrary, base metal and HAZ exhibited comparatively the similar value. On this experiment result Softening of HAZ is not occurred. in the heat affected zone, grain size repression be caused by chemical composition properties which a small quantity Al-Ti-B-N. Changing stress ratio near-threshold fatigue crack propagation experiments were carried out. According to this result, crack propagation velocity of the HAZ exhibited slower than the base metal and near-threshold value had increased at the HAZ. Finally accelerated cooling type TMCP steels were exhibited excellent mechanical properties in both strength and toughness.

Voltage Scaling 기반의 저전력 전류메모리 회로 설계

여성대,김성권,김종운,조태일,조승일 한국전자통신학회 2016 한국전자통신학회 논문지 Vol.11 No.2

무선통신시스템은 한정된 에너지를 갖는 배터리를 사용하기 때문에 저전력 회로로 구현되어야 하며, 이를 위하여 주파수와 상관없이 일정한 전력을 나타내는 전류모드 회로가 연구되어왔다. 본 논문에서는 초저전력 동작이 가능하도록 Dynamic Voltage Scaling 전원을 유도하며, 전류모드 신호처리 중 메모리 동작에서 저장된 에너지가 누설되는 Clock-Feedthrough 문제를 최소화하는 전류메모리 회로를 제안한다. 0.35µm 공정의 BSIM3 모델로 near-threshold 영역의 전원 전압을 사용한 시뮬레이션을 진행한 결과, 1MHz의 스위칭 동작에서 2µm의 메모리 MOS width, 0.3µm의 스위치 MOS width, 13µm의 dummy MOS width로 설계할 때, Clock-Feedthrough의 영향을 최소화시킬 수 있었으며 1.2V의 near-threshold 전원전압에서 소비전력은 3.7µW으로 계산되었다.