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Software Defined Radio 시스템을 위한 14비트 150MS/s 140㎽ 2.0㎟ 0.13㎛ CMOS A/D 변환기
유필선(Pil-Seon Yoo),김차동(Cha-Dong Kim),이승훈(Seung-Hoon Lee) 대한전자공학회 2008 電子工學會論文誌-SD (Semiconductor and devices) Vol.45 No.4
본 논문에서는 고해상도와 높은 신호처리속도, 저전력 및 소면적을 동시에 요구하는 Software Defined Radio (SDR) 시스템 응용을 위한 14비트 150MS/s 0.13㎛ CMOS ADC를 제안한다. 제안하는 ADC는 고해상도를 얻기 위한 특별한 보정 기법을 사용하지 않는 4단 파이프라인 구조로 설계하였고, 각 단의 샘플링 커패시턴스와 증폭기의 입력 트랜스컨덕턴스에 각각 최적화된 스케일링 계수를 적용하여 요구되는 열잡음 성능 및 속도를 만족하는 동시에 소모되는 전력을 최소화하였다. 또한, 소자부정합에 의한 영향을 줄이면서 14비트 이상의 해상도를 얻기 위해 MDAC의 커패시터 열에는 인접신호에 덜 민감한 3차원 완전 대칭 구조의 레이아웃 기법을 제안하였으며, 온도 및 전원 전압에 독립적인 기준 전류 및 전압 발생기를 온-칩 RC 필터와 함께 칩 내부에 집적하고 칩 외부에 C 필터를 추가로 사용하여 스위칭 잡음에 의한 영향을 최소화하였고, 선택적으로 다른 크기의 기준 전압 값을 외부에서 인가할 수 있도록 하였다. 제안하는 시제품 ADC는 0.13㎛ 1P8M CMOS 공정으로 제작되었으며, 측정된 DNL 및 INL은 14비트 해상도에서 각각 최대 0.81LSB, 2.83LSB의 수준을 보이며, 동적 성능은 120MS/s와 150MS/s의 동작 속도에서 각각 최대 64㏈, 61㏈의 SNDR과 71㏈, 70㏈의 SFDR을 보여준다. 시제품 ADC의 칩 면적은 2.0㎟ 이며 전력 소모는 1.2V 전원 전압에서 140㎽이다. This work proposes a 14b 150MS/s 0.13um CMOS ADC for SDR systems requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC employs a calibration-free four-step pipeline architecture optimizing the scaling factor for the input trans-conductance of amplifiers and the sampling capacitance in each stage to minimize thermal noise effects and power consumption at the target resolution and sampling rate. A signal- insensitive 3-D fully symmetric layout achieves a 14b level resolution by reducing a capacitor mismatch of three MDACs. The proposed supply- and temperature- insensitive current and voltage references with on-chip RC filters minimizing the effect of switching noise are implemented with off-chip C filters. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates a measured DNL and INL within 0.81LSB and 2.83LSB, at 14b, respectively. The ADC shows a maximum SNDR of 64㏈ and 61㏈ and a maximum SFDR of 71㏈ and 70㏈ at 120MS/s and 150MS/s, respectively. The ADC with an active die area of 2.0㎟ consumes 140mW at 150MS/s and 1.2V.
디지털 코드 오차 보정 기법을 사용한 15비트 50MS/s CMOS 파이프라인 A/D 변환기
유필선(Pil-Seon Yoo),이경훈(Kyung-Hoon Lee),윤근용(Kun-Yong Yoon),이승훈(Seung-Hoon Lee) 대한전자공학회 2008 電子工學會論文誌-SD (Semiconductor and devices) Vol.45 No.5
본 논문에서는 디지털 코드 오차 보정 기법을 사용한 15비트 50MS/s CMOS 파이프라인 ADC를 제안한다. 제안하는 ADC는 15비트 수준의 고해상도에서 면적과 전력 소모를 최소화하기 위해서 4단 파이프라인 구조를 사용하며 전체 ADC의 아날로그 회로를 변경하지 않고 첫 번째 단에 약간의 디지털 회로만을 추가하는 디지털 코드 오차 보정 기법을 적용한다. 첫 번째단에서 소자 부정합으로 인해 발생하는 코드 오차는 나머지 세 단에 의해 측정된 후 메모리에 저장되고 정상 동작 시 메모리에 저장된 코드 오차를 디지털 영역에서 제거하여 보정한다. 모든 MDAC 커패시터 열에는 주변 신호에 덜 민감한 3차원 완전 대칭 구조의 레이아웃 기법을 적용하여 소자 부정합에 의한 영향을 최소화하면서 동시에 첫 번째 단의 소자 부정합을 보다 정밀하게 측정하도록 하였다. 시제품 ADC는 0.18㎛ CMOS 공정으로 제작되었으며, 측정된 DNL 및 INL은 15비트 해상도에서 각각 0.78LSB 및 3.28LSB의 수준을 보이며, 50MS/s의 샘플링 속도에서 최대 SNDR 및 SFDR은 각각 67.2㏈ 및 79.5㏈를 보여준다. 시제품 ADC의 칩 면적은 4.2㎟ 이며 전력 소모는 2.5V 전원 전압에서 225㎽이다. This work proposes a 15b 50MS/s CMOS pipeline ADC based on digital code-error calibration. The proposed ADC adopts a four-stage pipeline architecture to minimize power consumption and die area and employs a digital calibration technique in the front-end stage MDAC without any modification of critical analog circuits. The front-end MDAC code errors due to device mismatch are measured by un-calibrated back-end three stages and stored in memory. During normal conversion, the stored code errors are recalled for code-error calibration in the digital domain. The signal insensitive 3-D fully symmetric layout technique in three MDACs is employed to achieve a high matching accuracy and to measure the mismatch error of the front-end stage more exactly. The prototype ADC in a 0.18㎛ CMOS process demonstrates a measured DNL and INL within 0.78LSB and 3.28LSB. The ADC, with an active die area of 4.2㎟, shows a maximum SNDR and SFDR of 67.2㏈ and 79. ㏈, respectively, and a power consumption of 225mW at 2.5V and 50MS/s.
( Pil Soo Sung ),( Si Hyun Bae ),( Jeong Won Jang ),( Do Seon Song ),( Hee Yeon Kim ),( Sun Hong Yoo ),( Chung Hwa Park ),( Jung Hyun Kwon ),( Myeong Jun Song ),( Chan Ran You ),( Jong Young Choi ),( 대한간학회 2011 Clinical and Molecular Hepatology(대한간학회지) Vol.17 No.4
Background/Aims: Enhanced replication of hepatitis C virus (HCV) is well described in the setting of moderate to severe immunosuppression. The aims of this retrospective study were to determine the incidence of enhanced HCV replication in hepatocellular carcinoma (HCC) patients undergoing transarterial chemolipiodolization (TACL) and to identify the factors associated with enhanced replication of HCV. The clinical pattern of enhanced HCV replication was compared with hepatitis B virus (HBV) reactivation during TACL. Methods: This study enrolled 49 anti-HCV-seropositive patients who were diagnosed with HCC between January 2005 and December 2010 and who underwent TACL using epirubicin and/or cisplatin with consecutive HCV RNA copies checked. For comparison, 46 hepatitis B surface antigen1-positive patients with HCC who were treated with TACL were also enrolled. The frequency, associated factors, and clinical outcomes of enhanced HCV replication were analyzed and compared with those of HBV reactivation during TACL. Results: Enhanced replication of HCV occurred in 13 (26.5%) of the 49 anti-HCV-seropositive patients during TACL. Of these 13 patients, 4 developed hepatitis, but none of the subjects developed decompensation due to the hepatitis. No significant clinical factors for enhanced HCV replication during TACL were found. Compared with HBV reactivation, the frequency of hepatitis attributed to enhanced HCV replication was significantly lower than that for HBV reactivation (8.2% vs. 23.9%, P=0.036). Conclusions: TACL can enhance HCV replication; however, the likelihood of hepatitis and decompensation stemming from enhanced HCV replication was lower than that for HBV reactivation in patients undergoing TACL. (Korean J Hepatol 2011;17:299-306)
Yeo, Seon Ju,Tu, Fuquan,Kim, Seung-hyun,Yi, Gi-Ra,Yoo, Pil J.,Lee, Daeyeon The Royal Society of Chemistry 2015 SOFT MATTER Vol.11 No.8
<P>Colloidal photonic crystals (CPCs) provide a convenient way to generate structural colour with high stability against degradation under environmental factors. For a number of applications including flexible electronic and energy devices, it is important to generate flexible structural colour that maintains its colour regardless of the angle of observation and the extent of mechanical deformation. However, it is challenging to simultaneously achieve these goals because anisotropy in typical CPC structures (<I>e.g.</I>, CPC films) tends to lead to angle-dependent photonic properties and also changes in the lattice constant due to mechanical deformation lead to changes in the photonic properties of CPCs. To overcome these challenges, we present a means of fabricating large-area free-standing films of CPC structures that exhibit angle- and strain-independent photonic characteristics. First, monodisperse double emulsions encapsulating colloidal crystal arrays are prepared using a microfluidic device. By inducing crystallization of highly charged polystyrene particles in the core of double emulsions using osmotic annealing, we generate angle independent colloidal photonic crystal (CPC) supraparticles. Moreover, the shape and crystallinity of the CPC supraparticles can be tuned by changing the concentration of salt in the solution used for osmotic annealing. Subsequently, an array of CPC supraparticles is embedded inside an elastomeric matrix to form a flexible free-standing film, which exhibits structural colours that are independent of viewing angles and externally applied strain.</P> <P>Graphic Abstract</P><P>A method to fabricate large-area free-standing films of colloidal photonic crystals which exhibit angle- and strain-independent structural colour is presented. <IMG SRC='http://pubs.rsc.org/services/images/RSCpubs.ePlatform.Service.FreeContent.ImageService.svc/ImageService/image/GA?id=c4sm02482f'> </P>