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RISS 인기검색어
- 검색키워드
- 저자 : Tuy Tan Nguyen (검색결과 7 건)
- 무료
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- 유료
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A Novel Performance Verification Approach of MIPI Camera Serial Interface 2
Tuy Tan Nguyen,Thang Xuan Pham,Phap Duong-Ngoc,Hanho Lee 한국차세대컴퓨팅학회 2022 한국차세대컴퓨팅학회 학술대회 Vol.2022 No.10
The explosive growth of embedded vision enables the use of imaging products such as cameras and displays in IoT and multimedia applications. Mobile Industry Processor Interface (MIPI) Camera Serial Interface 2 (CSI-2) is the most commonly used interface to connect image sensors or displays to application processors or SoCs in such applications. To ensure that imaging modules such as cameras work correctly when integrated into a system, verification processes such as bus functional verification and bus performance verification are essential. This paper introduces a bus performance verification approach for MIPI CSI-2. By evaluating the performance of a two-camera system with different video parameter sets, the best possible performance of the system is obtained. Simulation results show that the bandwidth utilization of each camera is more than 99.5%.
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Efficient Algorithm and Architecture for Elliptic Curve Cryptographic Processor
Nguyen, Tuy Tan,Lee, Hanho The Institute of Electronics and Information Engin 2016 Journal of semiconductor technology and science Vol.16 No.1
This paper presents a new high-efficient algorithm and architecture for an elliptic curve cryptographic processor. To reduce the computational complexity, novel modified Lopez-Dahab scalar point multiplication and left-to-right algorithms are proposed for point multiplication operation. Moreover, bit-serial Galois-field multiplication is used in order to decrease hardware complexity. The field multiplication operations are performed in parallel to improve system latency. As a result, our approach can reduce hardware costs, while the total time required for point multiplication is kept to a reasonable amount. The results on a Xilinx Virtex-5, Virtex-7 FPGAs and VLSI implementation show that the proposed architecture has less hardware complexity, number of clock cycles and higher efficiency than the previous works.
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Efficient Algorithm and Architecture for Elliptic Curve Cryptographic Processor
Tuy Tan Nguyen,Hanho Lee 대한전자공학회 2016 Journal of semiconductor technology and science Vol.16 No.1
This paper presents a new high-efficient algorithm and architecture for an elliptic curve cryptographic processor. To reduce the computational complexity, novel modified Lopez-Dahab scalar point multiplication and left-to-right algorithms are proposed for point multiplication operation. Moreover, bit-serial Galois-field multiplication is used in order to decrease hardware complexity. The field multiplication operations are performed in parallel to improve system latency. As a result, our approach can reduce hardware costs, while the total time required for point multiplication is kept to a reasonable amount. The results on a Xilinx Virtex-5, Virtex-7 FPGAs and VLSI implementation show that the proposed architecture has less hardware complexity, number of clock cycles and higher efficiency than the previous works.
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High-efficiency Low-latency NTT Polynomial Multiplier for Ring-LWE Cryptography
Tuy Nguyen Tan,Tram Thi Bao Nguyen,Hanho Lee 대한전자공학회 2020 Journal of semiconductor technology and science Vol.20 No.2
This paper presents a novel architecture to perform polynomial multiplication in ring learning with errors (ring-LWE) cryptosystems. By employing number theoretic transform (NTT) of the input polynomials simultaneously, the multiplication latency is significantly reduced. In addition, a multiple-path delay feedback (MDF) architecture is used to speed up the multiplication process. As a result, the proposed NTT multiplier offers a better value of area-latency product compared with that of previous studies. The simulation results for the security parameters n = 512 and q = 12,289 on Xilinx Virtex-7 FPGA show that the proposed multiplier uses only about 8.69% of the number of clock cycles required by previous works to completely perform the polynomial multiplication. Furthermore, the obtained area-latency product value of the proposed architecture is less than 45.3% of that of previous works.
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High-performance Ring-LWE Cryptography Scheme for Biometric Data Security
Tuy Nguyen Tan,Hanho Lee 대한전자공학회 2018 IEIE Transactions on Smart Processing & Computing Vol.7 No.2
The rapid growth of using biometric devices for authentication and the fast development of the quantum computer means stronger and more reliable security services are needed for biometric data protection. This paper presents a novel ring-learning with errors (ring-LWE) cryptography scheme and a post-quantum cryptosystem for biometric data security. By using parallel multiplication and parallel addition in ring-LWE cryptography operations, the total encryption and decryption time can be significantly reduced. As a result, the proposed highperformance ring-LWE cryptography scheme outperforms existing cryptosystems in terms of processing time for text message encryption and decryption. Moreover, compared to the scheme implemented on a central processing unit (CPU), the proposed scheme on a graphics processing unit (GPU) can reduce encryption and decryption times for biometric images by up to 20 times and four times, respectively. A performance analysis of entropy and the similarity of the encrypted image generated by the proposed scheme also demonstrate improvement in the confidentiality of the cipher image, compared to previous works.
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SRAM 의 읽기 및 쓰기 동작을 위한 Assist Block
( Tuy Nguyen Tan ),손민한 ( Minhan Shon ),추현승 ( Hyunseung Choo ) 한국정보처리학회 2013 한국정보처리학회 학술대회논문집 Vol.20 No.1
Static Random Access Memory (SRAM) using CMOS technology has many advantages. It does not need to refresh every certain time, as a result, the speed of SRAM is faster than Dynamic Random Access Memory (DRAM). This is the reason why SRAM is widely used in almost processors and system on chips (SoC) which require high processing speed. Two basic operations of SRAM are read and write. We consider two basic factors, including the accuracy of read and write operations and the speed of these operations. In our paper, we propose the read and write assist circuits for SRAM. By adding a power control circuit in SRAM, the write operation performed successfully with low error ratio. Moreover, the value in memory cells can be read correctly using the proposed pre-charge method.
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High-Throughput Multi-Threaded Non-binary LDPC Decoder Architecture
Thang Xuan Pham,Tuy Nguyen Tan,Phap Duong-Ngoc,Huyen Pham Thi,Hanho Lee 한국차세대컴퓨팅학회 2021 한국차세대컴퓨팅학회 학술대회 Vol.2021 No.11
This paper introduces an efficient non-binary low-density parity-check (NB-LDPC) decoder architecture, in terms of increasing decoding throughput. By taking advantages of non-binary quasi-cyclic LDPC codes, a new layered decoding algorithm and corresponding efficient hardware architecture are introduced. The proposed method can improve parallelism in decoding estimations of NB-LDPC decoder while remaining error-correcting performance. The implementations results confirmed that the proposed decoder with two threads can achieve a throughput of about 2.78 Gbps, which is around 1.63 times faster than that of the state-of-the-art decoder at almost the same hardware efficiency.
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