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박준규(J. K. Park),심현철(H. C. Shim),박종태(J. T. Park),유종근(C. G. Yu) 대한전기학회 2006 대한전기학회 학술대회 논문집 Vol.2006 No.10
This paper describes a 2.5V, 320㎒ low-noise and low-power Phase Locked Loop(PLL) using a noise-rejected Voltage Controlled ring Oscillator(VCO) fabricated in a TSMC 0.25㎛ CMOS technology. In order to improve the power consumption and oscillation frequency of the PLL, The VCO consist of three-stage fully differential delay cells that can obtain the characteristic of high speed, low power and low phase noise. The VCO operates at 7㎒-670㎒. The oscillator consumes 1.58㎃ from a 320㎒ frequency and 2.5V supply. When the PLL with fully-differential ring VCO is locked 320㎒, the jitter and phase noise measured 26㎰ (rms), 157㎰ (p-p) and -97.09㏈ at 100㎑ offset. We introduce and analysis the conditions in which ring VCO can oscillate for low-power operation.