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유재택 대한전자공학회 1996 CAD 및 VLSI 설계연구회지 Vol.5 No.1
VLSI chips suffer from exaggerated clock skew problems when the clock rate reaches several hundred MHz. To solve these problems, we, propose the use of counterflow-clocking in which the clocks are distributed in a direction opposite to the data flow direction by employing hack-propagating clock signals amplified b5 a chain of inverters. This paper introduces Counterflow-Clocked(C²) Pipelining and discusses its usefulness and limitations to build large and high speed VLSI chips. It also presents the design of an image compression chip set to implement subband vector quantization that can handle HDTV data rates with reasonable VLSI chip sizes, The major advantages of this new pipelining are: easier distribution of high speed clocks, shorter clock period due to the absence of global clock signals, natural use of dynamic latches, less internally generated noise due to uniformly distributed latch operations, etc. Composition methods were developed. The use of these methods enabled us to build a system with two-dimensional data-flow in C² pipelining employing a tree of inverter chains fer clock distribution. C² pipelining was used to design an IDTV chip set with several design innovations, demonstrating the applicability and viability of the technology.
잡음제거 및 Threshold 갱신을 통한 영상보안감시용 움직임 검출 알고리즘의 개선
유재택 안양대학교 2001 논문집 Vol.20-21 No.-
원격 보안감시용 camera에서 움직임 검출을 효과적으로 수행하기 위하여 잡음제거 기법과 pixel threshold 갱신 기법을 제안하여 차영상 움직임검출 알고리즘을 개선하였다. 이 기법들을 동시에 적용함으로서 영상잡음에 대한 민감도를 해결하였다. 환경요소인 조명변화시 차영상 알고리즘은 움직임검출이 작동되나 이에 적응하기 위하여 움직임검출 보류와 기준 frame 갱신을 통해 조명 변화에 민감한 문제를 해결하였다. 제작된 장치의 실험을 통하여 개선된 알고리즘은 현격한 잡음 발생 억제와 제거 효과를 보였으며 조명변화에도 적응하는 것을 확인하였다. To generate motion detections effectively at remote security supervision cameras, motion detection algorithm using difference images is improved by our proposed noise cancellation technique and pixel threshold update technique. Applying both techniques altogether, the sensitivity to the image noises are much reduced. Since illumination variations cause motion detections with difference image method, deferment of detection and update of reference frame techniques are applied to avoid unnecessary detections. Our experimentation showed that the improved algorithm resulted in unequal noise reductions-and-cancellations and adaptation to illumination variations.
AYM망에서 ABR 서비스의 공정 대역폭 할당을 위한 퍼지 전송률 제어 기법
유재택,김용우,김영한,이광형 한국통신학회 1997 韓國通信學會論文誌 Vol.22 No.5
본 논문에서는 ATM 네트워크에서의 접속된 ABR 서비스에 대해 공정한 대역폭을 할당하는 새로운 비율 기반 전송률 제어 알고려즘을 제안한다. 기존 ABR 서비스에서는 일정률로 전송률을 증가, 감소를 하면서 대역폭을 할당하나 제안된 알고리즘에서는 이용 가능한 대역폭을 퍼지 추론을 하여 접속된 호에 대해 전송률을 공평하게 분할하는 기법이다. 퍼지 추론은 입력 변수로 버퍼 상태, 버퍼 변화율을 사용하고 출력 변수로 전체 전송률을 사용한다. 이 추론된 결과값은 동작 중에 있는 ABR 서비스 호에 공평하게 분배되어 진다. 모의 실험 결과 기존의 E EPRCA 방식보다 제안된 방식이 링크 효율면에서 RIF, RDF가 1일 경우 0.17%, 1/4 경우 6%, 1/16 경우 38.6%, 1/32 경우 82.4%의 향상을 보였다. In this paper, we propose the new rate-based transmission rates control algorithm that allocates the fair band-width for ABR service in ATM network. In the traditional ABR service, bandwidth is allocated with constant rate increment or decrement, but in the proposed algorithm, it is allocated fairly to the connected calls by the fuzzy inference of the available bandwidth. The fuzzy inference uses buffer state and the buffer variant rate as the input variables, and uses the total transmission rate as a output variable. This inference a bandwidth is fairly distributed over all ABR calls in service. By simmulation, we showed that the proposed method improved 0.17% in link effectiveness when RIF, RDF is 1/4, 38.6% when RIF, RDF 1/16, and 82.4% when RIF, RDF 1/32 than that of the traditional EFPCA.
A low-power and large-swing edge combiner for a DLL-based frequency synthesizer
유재택 안양대학교 산업기술연구소 2004 自然科學硏究 Vol.11 No.1
An edge combiner using a differential pseudo-NMOS logic is proposed and generalized for a DLL-based frequency synthesizer. This combiner creates a multiplied frequency by digitally combing outputs form the DLL in AND-OR structure. The use of a pseudo-NMOS circuit enables the EC to satisfy a large output swing and low power consumption simultaneously. In addition, this EC can exclude use of spiral inductors indispensable for conventional combiner. Simulation results show that the output swing of the edge combiner is increased by 87% and its power dissipation is reduced by 89.8% in comparison to those of its conventional version.