Global Planarization Characteristics of Shallow Trench Isolation-Chemical Mechanical Polishing Process with and without Reverse Moat Etch Step

서용진,Chul-Bok Kim,박진성,Sang-Yong Kim,Sung-Woo Park,이우선 한국물리학회 2003 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.42 No.III

The reverse moat etch process has been used for the shallow trench isolation (STI)-CMP process with conventional low selectivity slurries between SiO$_2$ and Si$_3$N$_4$ film. The process became more complex, and the defects seriously increased. Because the removal rates of each region were different in the STI-CMP process, damage might occur on active regions in case of an excessive CMP process, whereas, in the case of an insufficient CMP process, some nitride might remain on the active region after nitride strip process due to unpolished oxide residues. In this paper, we investigated the CMP characteristics of STI structure with a reverse moat step. Then, we studied the direct STI-CMP process without reverse moat etch step using high selectivity slurry (HSS). As our experimental results, it was possible to achieve good global planarization characteristics without the complicated reverse moat process, and therefore the STI-CMP process could be simplified and greatly improved.

A Study on the Electrochemical and the Chemical Mechanical Polishing Behaviors of W and Ti Film

서용진,Sung-Woo Park 한국물리학회 2007 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.50 No.3

In this paper, the chemical mechanical polishing (CMP) performances of tungsten (W) and titanium (Ti) films according to the oxidizer content were studied through an electrochemical corrosion analysis. In order to investigate the electrochemical polishing behavior of the W and the Ti films, we used an alumina (Al$_2$O$_3$)-based tungsten slurry with a H$_2$O$_2$ oxidizer for CMP test. As an experimental result, for the case of 5 vol\% added oxidizer, the removal rates were improved, and a good polishing selectivity of 1.4 : 1 was obtained, which means that the oxidizer with the highest removal rate has a high dissolution rate due to the predominant electrochemical corrosion effects. Therefore, we conclude that the CMP characteristics of W and Ti strongly depend on the amounts of H$_2$O$_2$ oxidizer added

실리카 연마제가 첨가된 재활용 슬러리를 사용한 2단계 CMP 특성

서용진,이경진,최운식,김상용,박진성,이우선 한국전기전자재료학회 2003 전기전자재료학회논문지 Vol.16 No.9

Recently, CMP (chemical mechanical polishing) technology has been widely used for global planarization of multi-level interconnection for ULSI applications. However, COO (cost of ownership) and COC (cost of consumables) were relatively increased because of expensive slurry. In this paper, we have studied the possibility of recycle of roused silica slurry in order to reduce the costs of CMP slurry. The post-CMP thickness and within-wafer non-uniformity (WIWNU) wore measured as a function of different slurry composition. As an experimental result, the performance of reused slurry with annealed silica abrasive of 2 wt% contents was showed high removal rate and low non-uniformity. Therefore, we propose two-step CMP process as follows , In tile first-step CMP, we can polish the thick and rough film surface using remaked slurry, and then, in the second-step CMP, we can polish the thin film and fine pattern using original slurry. In summary, we can expect the saying of high costs of slurry.

실리콘 양자전자소자의 전류-전압 및 컨덕턴스 특성

서용진 한국전기전자학회 2019 전기전자학회논문지 Vol.23 No.3

The silicon-adsorbed oxygen(Si-O) superlattice grown by ultra high vacuum-chemical vapor deposition(UHV-CVD)was introduced as an epitaxial barrier for silicon quantum electron devices. The current-voltage (I-V) measurementresults show the stable and good insulating behavior with high breakdown voltage. It is apparent that the Si-Osuperlattice can serve as an epitaxially grown insulating layer as possible replacement of silicon-on-insulator(SOI). Thisthick barrier may be useful as an epitaxial insulating gate for field effect transistors(FETs). The rationale is that itshould be possible to fabricate a FET on top of another FET, moving one step closer to the ultimate goal of futuresilicon-based three-dimensional integrated circuit(3DIC). 초고진공 화학기상증착장치(UHV-CVD)에 의해 성장된 실리콘-흡착된 산소(Si-O) 초격자가 실리콘 양자전자소자를 위한에피택셜 장벽으로 소개되었다. 전류-전압 측정 결과 높은 브레이크다운 전압을 갖는 매우 안정하고 양호한 절연특성을 나타내었다. 에피택셜 성장된 Si-O 초격자는 SOI(silicon on insulator)를 대체할 수 있는 절연층으로도 사용될 수 있음을 보여준다. 이 두꺼운 장벽은 전계효과트랜지스터(FET)의 절연 게이트로 유용하게 사용될 수 있어 FET 위에 또 다른 FET를 제작할 수 있으므로 미래 실리콘계 3차원 집적회로의 궁극적인 목표에 한층 더 다가갈 수 있는 가능성을 보여주는 것이다.

물류이동거리 최소를 위한 유전자 알고리즘 기반 FAB Facility 배치

서용진,최진영 한국산업경영시스템학회 2016 한국산업경영시스템학회 학술대회 Vol.2016 No.추계

표면이온주입에 의한 LDD-nMOSFET의 핫 캐리어 신뢰성 개선에 대한 연구

서용진 대불대학교 1998 論文集 Vol.4 No.1

Reduction of hot carrier degradation in MOS devices has been one of the most serious concerns for MOS-ULSIs. In this paper, three types of LDD structure for suppression of hot carrier degradation, such as spacer-induced degradation and decrease of performance due to increase of series resistance will be investigated. LDD-nMOSFETs used in this study had three different drain structure, (1) conventional Surface type LDD(SL), (2) Buried type LDD(BL), (3)Surface Implantation type LDD(SI). As a results, the surface implantation type LDD structure showed that improved hot carrier lifetime to comparison with conventional surface and buried type LDD structure.

반도체-원자 초격자의 광전자 특성

서용진,정소영,박성우 대불대학교 2002 論文集 Vol.8 No.1

Optoelectronic characteristics of the superlattice as a function of deposition temperature and annealing conditions have been studied. The nanocrystalline silicon/adsorbed oxygen superlattice formed by molecular beam epitaxy (MBE) system. Consequently, the experimental results of superlattice with multilayer Si-O structure showed the stable photoluminescence(PL) and good insulating behavior with high breakdown voltage. This is very useful promise for Si-based optoelectronic and quantum device as well as for the replacement of silicon-on-insulator(SOI) in ultra high speed and lower power CMOS devices in the future, and it can be readily integrated with silicon ULSI processing.

반경험적 스케일 방법을 사용한 0.35 μm LDD-nMOSFET의 핫 캐리어 현상 억제를 위한 공정설계에 관한 연구

서용진,안태현,이경태 대불대학교 1998 論文集 Vol.4 No.1

This paper grasped trends of hot-corrier and punchthrough phenomena as a variation of some process parameters such as LDD doses (P), spacer lengths, channel doses(BF_(2)) and V_(T) adjusting channel implantation energies using Design Trend Curve(DTC). As the LDD dose increased, hot-carrier phenomena became more severe and punchthrough phenomenon was deteriorated. As increasing channel dose (BF_(2)), hot-carrier phenomenon was aggravated in contrast with punchthrough phenomenon which was improved. The model was proved by two dimensional electrical characteristics including generation of impact ionization rate and distribution of electric field with simulation. It was used to TSUPREM-IV and MEDICI for processing and device simulation, respectively.

PZT 박막의 화학·기계적 연마 특성

서용진,이우선 대한전기학회 2006 전기학회논문지C Vol.55 No.12C

- In this paper, we first applied the chemical mechanical polishing (CMP) process to the planarization of ferroelectric film in order to obtain a good planarity between electrode and ferroelectric film. Pb1.1(Zr0.52Ti0.48)O3 (shortly PZT) ferroelectric film was fabricated by the sol-gel method. And then, we compared the structural characteristics before and after CMP process of PZT films. Removal rate, WIWNU% and surface roughness have been found to depend on slurry abrasive types and their hardness, especially, surface roughness and planarity were strongly depends on its pH value. A maximum in the removal rate is observed in the silica slurry, in contrast with the minimum removal rate occurs at ceria slurry. We found that the surface roughness of PZT films can be significantly reduced using the CMP technique.

CMP 공정의 재현성 확보를 위한 공정제어 범위의 결정

서용진,정소영,김철복,박성우,이경진,김기욱,박창준 대불대학교 2002 大佛大學校大學院 硏究論文集 Vol.- No.1

To achieve the ULSI goals of higher density and greater performance, STI(shallow trench isolation)-CMP(chemical mechanical polishing) process has been attracted. Recently, the direct STI-CMP process without the conventional complex reverse moat etch process has established by using slurry additive with the high selectivity between SiO2 and Si3N4 films for the purpose of process simplification and in-situ EPD(end point detection). However, STI-CMP process has various defects such as nitride residue, torn oxide and demage of silicon active region. Also, it was difficult to assure the suitable process margin in the STI-CMP process. To solve these problems, in this paper, we discussed to determine the control limit of process, which can entirely remove the oxide on nitride film from the most area of high density as reducing the damage of dense moat area and minimizing dishing effect in the large field area. We, also, evaluated the wafer-to-wafer thickness variation and the day-by-day reproducibility of STI-CMP process after repeatable tests.