동결 보존에 의한 돼지 정자 세포질 칼슘 신호의 변화

이선우,이옥화,김준철,명평근,박창식,우선희 충남대학교 형질전환복제돼지연구센터 2007 논문집 Vol. No.10

Although mammalian sperms are cryopreserved for in vitro fertilization a process of cryopreservation decreases the fertility. Acrosome reaction requires depolarization-induced ca^(2+) influx and ca^(2+) releases from the ca^(2+) stores. To examine whether the cellular ca^(2+) mobilization is altered by a sperm cryopreservation we compared cytosolic ca^(2+) signals between fresh and cryopreserved pig sperms using confocal ca^(2+) imaging. The magnitudes of depolarization-induced ca^(2+) increases were significantly smaller in cryopreserved sperms. Exposures to 10 mM caffeine or 5 μM thapsigargin elicited less ca^(2+) increases in the cryopreserved sperms compared to fresh sperms. In addition, progesterone-triggered ca^(2+) rises, that are thought to enhance acrosome reaction, were completely abolished in the cryopreserved sperms. These results suggest that storage and(/or) release of ca^(2+) from the intracellular ca^(2+) stores in pig sperms are significantly impaired by the process of cryopreservation.

유동적 결합성을 가지는 다중프로세서의 구조와 성능분석

선우 명훈(Sunwoo Myung Hoon) 한국정보과학회 1994 정보과학회논문지 Vol.21 No.12

일반적으로 다중프로세서에서 프로세서들간의 데이타 공유를 위하여 두가지 방식이 주로 쓰이는데 이는 메시지 전달 방식 및 공유 기억소자 방식이다. 그러나 전자는 통신부담이 결점이며 후자는 공유기억소자 분쟁의 단점이 있다. 또한 비효율적인 데이타 입출력 구조도 성능향상에 있어 제한사항이다. 본 논문에서는 위의 단점들을 경감시킬 수 있는 유동적인 연결구조를 갖는 새로운 다중프로세서 (Flexibly Coupled Multiprocessors)를 제안한다. 이 다중프로세서의 구현을 위하여 가변길이 기억소자 (Variable Address Space Memory)를 제안하는데 이는 이웃한 기억소자 모듈들이 필요에 따라 재분할이 가능한 버스구조에 의하여 하나의 기억소자 모듈이 될 수 있다. 따라서 이 가변길이 기억소자 모듈들은 공유 기억소자 또는 비공유 기억소자로 사용된다. 제안하는 다중프로세서의 정량적 모델을 정립, 분석하였고, 상용의 하이퍼큐브 구조 다중프로세서인 Inter's Personal SuperComputer (iPSC)를 이용하여 시뮬레이션 하였다. 성능평가를 위하여 병렬처리 알고리즘들을 개발하여 실지로 iPSC상에서 구현하였으며 제안하는 다중프로세서의 정량적 모델을 이용, 시뮬레이션을 통한 비교 분석을 수행하였다. 실험결과 제안하는 다중프로세서가 iPSC보다 성능에서 월등함을 입증하였다. Two hardware mechanisms are mainly used for data sharing among processors in existing multiprocessors: message passing in loosely coupled multiprocessors and shared memory in tightly coupled multiprocessors. The former has communication overhead and the latter has shared memory contention. Moreover, inefficient data input and output (I/O) schemes are also limitations on performance. This paper proposes a new architecture, called the Flexibly (Tightly/Loosely) Coupled Multiprocessors (FCM), to alleviate these disadvantages. A variable address space memory scheme, in which a set of adjacent memory modules can be merged by a dynamically partitionable bus, is proposed to realize FCM. Computational models of FCM are established, quantitatively analyzed and simulated on the iPSC (Intel's Personal SuperComputer), a hypercube multiprocessor. Parallel algorithms for region labeling and median filtering are implemented on the iPSC and simulated on FCM. The performance of FCM shows remarkable improvement over that of the iPSC.

New Cost-Effective Simplified Euclid’s Algorithm for Reed-Solomon Decoders

Baek, Jaehyun,Sunwoo, Myung Hoon Springer-Verlag 2013 Journal of signal processing systems Vol.71 No.2

움직임 추정 전용 프로세서를 위한 효율적인 루프 가속기

하재명(Jae Myung Ha),정호선(Ho Sun Jung),선우명훈(Myung Hoon Sunwoo) 대한전자공학회 2013 전자공학회논문지 Vol.50 No.7

본 논문은 움직임 추정 전용 프로세서를 위한 효율적인 루프 가속기를 제안한다. 실제로 움직임 추정 알고리즘은 복잡하고 다양한 순환 명령어들을 포함하고 있다. 본 논문에서는 효율적인 하드웨어 루프 명령어들을 지원하기 위해서, 네 개의 루프 명령어와 그에 따른 하드웨어 구조를 소개한다. 검증 결과 제안된 루프 가속기가 early-termination을 이용한 움직임 추정 시 비교명령어와 조건부 점프명령어를 갖고 있는 전형적인 구현 방법과 비교했을 때 평균 명령어 사이클 수를 약 29% 줄일 수 있다는 것을 보여준다. 제안된 움직임 추정 전용 프로세서 루프 가속기는 프로그램 메모리의 접근 빈도를 상당히 줄일 수 있고, 전력 소모를 많이 절약할 수 있다. 따라서, 제안된 루프 가속기는 전력 소모가 적고, 유연한 움직임 추정에 적합하다. This paper proposes an efficient loop accelerator for a motion estimation specific instruction-set processor. ME algorithms in nature contain complex and multiple loop operations. To support efficient hardware (HW) loop operations, this paper introduces four loop instructions and their specific HW architecture. The simulation results show that the proposed loop accelerator can reduce about 29% average instruction cycles for ME early-termination schemes compared with typical implementation having a combination of compare and conditional jump instructions. The proposed loop accelerator of the motion estimation specific instruction-set processor can significantly reduce the number of program memory accesses and greatly save power consumption. Hence, it can be quite suitable for low power and flexible ME implementation.

A New OFDM Transmission Scheme Using DFT Code Multiplexing

SeongKeunOh,KiSeubLee,Myung Hoon Sunwoo 에스케이텔레콤 (주) 2002 Telecommunications Review Vol.12 No.4

We propose a new orthogonal frequency division multiplexing transmission scheme using orthogonal code multiplexing. This scheme makes all modulation symbols have the same reliability even in a frequency selective fading channel, through a distributed transmission of each symbol over the whole effective subcarriers using a distinct orthogonal code. As an appropriate set of orthogonal multiplexing codes, we use the set of discrete Fourier transform code sequences that hold the orthogonality irrespective of the length. Using this set, we also can greatly reduce the peak-to-average-power ratio (PAR) of the resulting signal. Simulation results show that the proposed scheme can significantly reduce the required signal-to-noise ratio at a given bit error rate over the existing schemes. The scheme can maintain the PAR within a reasonable range of about 6dB even up to 512 subcarriers and works well even with PAR clipping of 1.5dB.

Novel Digital Signal Processing Unit Using New Digital Baseline Wander Corrector for Fast Ethernet

Hong, Juhyung,Baek, Jaehyun,Sunwoo, Myung Hoon Springer-Verlag 2010 Journal of signal processing systems Vol.61 No.2

MESIP: A Configurable and Data Reusable Motion Estimation Specific Instruction-Set Processor

Sung Dae Kim,Myung Hoon Sunwoo IEEE 2013 IEEE Transactions on Circuits and Systems for Vide Vol.23 No.10

<P>This paper proposes a new motion estimation (ME)-specific instruction-set processor (MESIP) with a novel search scan order with high data reusability, to efficiently implement various advanced ME algorithms. The proposed ME-specific instructions can be selectively used for ME algorithms. The novel data-reusing search scan order, called center biased search scan (CBSS), exploits the symmetry of the search pattern to reduce redundant data loading on MESIP by about 26.9% and 16.1% compared with raster scan and snake scan, respectively. MESIP has been implemented with IBM's 90-nm CMOS technology and has 203 K gates excluding memory. Simulation results show that the proposed MESIP can reduce the number of required instructions by up to 18.9% compared with existing ME processors. Moreover, MESIP achieves comparable performance even with ME ASICs and hence may be quite suitable for a low-power and high-performance ME implementation.</P>

Three-Parallel Reed-Solomon Decoder Using S-DCME for High-Speed Communications

Lee, Jae Do,Sunwoo, Myung Hoon Springer-Verlag 2012 Journal of signal processing systems Vol.66 No.1

New Frame Rate Up-Conversion Algorithms With Low Computational Complexity

Un Seob Kim,Myung Hoon Sunwoo IEEE 2014 IEEE transactions on circuits and systems for vide Vol.24 No.3

<P>This paper proposes a new frame rate up-conversion (FRUC) algorithm to reduce the computational complexity and to improve the peak signal-to-noise ratio (PSNR) performance. The proposed FRUC algorithm includes prediction-based motion vector smoothing (PMOS), partial average-based motion compensation (PAMC), and intrapredicted hole interpolation (IPHI). PMVS can efficiently remove outliers using motion vectors of neighboring blocks and PAMC performs motion compensation with the region-based partial average to reduce blocking artifacts of the interpolated frames. For hole interpolation, IPHI uses intraprediction of H.264/AVC to eliminate blurring and also uses the fixed weights implemented using only shift operations, which result in low computational complexity. Compared to the existing algorithms, which use bilateral motion estimation, the proposed algorithm improves the average PSNR of the interpolated frames by 3.44 dB and lowers PSNR performance only by 0.13 dB than the existing algorithm that employs unilateral ME; however, it can significantly reduce the computational complexity of FRUC about 89.3% based on the absolute difference.</P>

Low Complexity Synchronizer Using Common Autocorrelator for DVB-S2 System

Jang Woong Park,Myung Hoon Sunwoo,Pan Soo Kim,Dae-Ig Chang 대한전자공학회 2009 Journal of semiconductor technology and science Vol.9 No.4

This paper presents an efficient synchronizer architecture using a common autocorrelator for Digital Video Broadcasting via Satellite, Second generation (DVB-S2). To achieve the required performance under the worst channel condition and to implement the efficient H/W resource utilization of functional synchronization blocks, we propose a new efficient common autocorrelator structure. The proposed architecture can decrease about 92% of multipliers and 81% of adders compared with the direct implementation. Moreover, the proposed architecture has been thoroughly verified in XilinxTM Virtex IV and R&STM SFU (Signaling and Formatting Unit) broad-cast test equipment.