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장영조 한국기술교육대학교 1997 論文集 Vol.4 No.1
This paper represents a Register Transfer(RT) level architecture design for a DCT chip. The architecture exploits highly parallel and pipelined scheme to apply it to high speed image applications. Using a distributed arithmetic instead of a multiplication, the chip area can be reduced dramatically. Two separate NxN 1D-DCT/IDCT, a transpose RAM, and two controllers are the basic structure. With variations to bit width of input/output, the modulized 1D-IDCT structure can be adopted easily to 2D-IDCT, 1D-DCT, and 2D-DCT. The proposed architecture for IDCT is modeled with VHDL and synthesized to gate level. The simulation result by VHDL shows that the designed architecture can handle in image compression/decompression with 100MHz clock frequency.
장영조,방정배 한국기술교육대학교 2003 論文集 Vol.10 No.1
In this paper, we improved an architecture of 2D-DWT and obtained the result of reduction hardware cost by means of sharing registers and other hardwares. Also, it makes easy to expand filter lengths using regular data flow structure. We obtained 27.5% reduction of hardware cost by proposed architecture. The improved structure is designed by using VHDL and implemented to FPGA. Finally, the result of analysis has been confirmed by showing on TFT LCD.
방사선 조사에 따른 LDPE박막의 결정구조에 미치는 특성
장영조,박재웅,김종석 大田産業大學校 2000 한밭대학교 논문집 Vol.17 No.1
LDPE pelet is distilled to make 0.5 Wt% solutions and fabricated as LDPE thin film by dropping the solution onto glass substrate, and then annealed the film to be crystalline. The structure is observed as crystalline regions and non-crystalline regions. The crystalline region is exposed at radiation and as the result, there appeared degradation at the total region of the crystal structure. It is considered therefore that radiation exposure at the crystal structure is badly effected on insulation property and lifetime of materials.