Performance Comparison of Multi-level Coding Schemes for NAND Flash Memory

Jieun Oh,Seokju Han 대한전자공학회 2018 IEIE Transactions on Smart Processing & Computing Vol.7 No.6

Emerging three-dimensional (3D) NAND flash memory devices support new input/output (I/O) modes in which devices can program/read multiple pages sharing a common word line at the same operating time. The new I/O modes enable error-control systems to apply non-binary coding techniques, which are known to achieve capacity-approaching performance in a high signal-to-noise ratio (SNR) regime in conjunction with high-order modulations for NAND storage devices. This paper compares the performance of a number of multi-level-coding/multistage-decoding (MLC/MSD) schemes for NAND flash memory applications. By applying MLC/MSD techniques, it is possible to minimize the code rate loss caused by using the same code designed for the bit level of a page with the highest error rate equal to the remaining bit level of the pages. One considered scheme is an MLC/MSD method applied to 1D and 2D constellations with Bose-Chaudhuri-Hocquenghem (BCH) component codes. Another scheme compared is a special trellis-coded modulation (TCM) method with extra-strong error correction applied to subset labeling bits via Reed-Solomon (RS) code concatenation. In this paper, a new performance analysis method based on semi-analytical block-multinomial modeling is proposed to provide a simpler way to handle correlated error in TCM output. The analytical error rate results and semi-analytical error rate results based on the block multinomial model with the TCM scheme all indicate significant performance advantages from MLC/MSD schemes relative to the baseline BCH coding method.

Flexible WOM Codes for NAND Flash Memory Based on Raptor-Like Codes

전보환,곽희열,노종선,박호성 한국통신학회 2018 Journal of communications and networks Vol.20 No.2

Write-once memory (WOM) codes aim to extend the lifetimeand improve the writing efficiency of storage devices such asNAND flash memory by reducing the number of erase operations. In this paper, a new rewriting scheme for NAND flash memory isproposed, which supports two writes (or only one rewrite) and allowsthe second write incrementally done multiple times by usingraptor-like codes as rate-compatible (RC) low-density generatormatrix (LDGM) codes. The proposed scheme improves writing efficiencyof the NAND flash memory when combined with a properpage selection method. It is verified via numerical analysis that theproposedWOM codes outperform the conventionalWOM codes interms of writing efficiency.

에러 보정 코드를 이용한 비동기용 대용량 메모리 모듈의 성능 향상

안재현,양오,연준상 한국반도체디스플레이기술학회 2020 반도체디스플레이기술학회지 Vol.19 No.3

NAND flash memory is a non-volatile memory that retains stored data even without power supply. Internal memory used as a data storage device and solid-state drive (SSD) is used in portable devices such as smartphones and digital cameras. However, NAND flash memory carries the risk of electric shock, which can cause errors during read/write operations, so use error correction codes to ensure reliability. It efficiently recovers bad block information, which is a defect in NAND flash memory. BBT (Bad Block Table) is configured to manage data to increase stability, and as a result of experimenting with the error correction code algorithm, the bit error rate per page unit of 4Mbytes memory was on average 0ppm, and 100ppm without error correction code. Through the error correction code algorithm, data stability and reliability can be improved.

휴대장치를 위한 고속복원의 프로그램 코드 압축기법

김용관(Yongkwan Kim),위영철(Youngcheul Wee) 한국정보과학회 2010 정보과학회논문지 : 소프트웨어 및 응용 Vol.37 No.11

대부분의 휴대기기는 보조 기억장치로 NAND flash 메모리를 사용하고 있다. 또한, firmware의 크기를 줄이고 NAND flash로부터 주기억장치로 로딩하는 시간을 줄이기 위해서 압축된 코드를 NAND flash에 저장한다. 특히, 압축된 코드는 매우 빠르게 해제가 되어야 demand paging이 적용 가능하게 된다. 본 논문에서는 이를 위하여 새로운 사전식 압축 알고리즘을 제안한다. 이 압축방식은 기존의 LZ형식과는 다르게 현재 압축하고자 하는 명령어(instruction)가 참조된 명령어와 같지 않을 경우, 프로그램 코드의 명령어의 특성을 이용하여 두 명령어의 배타 논리합(exclusive or) 값을 저장하는 방식이다. 또한, 압축 해제 속도를 빠르게 하기 위해서, 비트 단위의 연산을 최소화한 압축형식을 제공한다. 실험결과 zlib과 비교해서 최대 5배의 압축해제 속도와 4%의 압축률 향상이 있었으며, 이와 같이 매우 빠른 압축해제 속도에 따라 부팅(booting) 시간이 10~20% 단축되었다. Most mobile devices use a NAND flash memory as their secondary memory. A compressed code of the firmware is stored in the NAND flash memory of mobile devices in order to reduce the size and the loading time of the firmware from the NAND flash memory to a main memory. In order to use a demand paging properly, a compressed code should be decompressed very quickly. The thesis introduces a new dictionary based compression algorithm for the fast decompression. The introduced compression algorithm uses a different method with the current LZ method by storing the “exclusive or” value of the two instructions when the instruction for compression is not equal to the referenced instruction. Therefore, the thesis introduces a new compression format that minimizes the bit operation in order to improve the speed of decompression. The experimental results show that the decoding time is reduced up to 5 times and the compression ratio is improved up to 4% compared to the zlib. Moreover, the proposed compression method with the fast decoding time leads to 10-20% speed up of booting time compared to the booting time of the uncompressed method.

Development of stability maps for flashing-induced instability in a passive containment cooling system for iPOWER

Lim, Sang Gyu,No, Hee Cheon,Lee, Sang Won,Kim, Han Gon,Cheon, Jong,Lee, Jae Min,Ohk, Seung Min Korean Nuclear Society 2020 Nuclear Engineering and Technology Vol.52 No.1

A passive containment cooling system (PCCS) has been developed as advanced safety feature for innovative power reactor (iPOWER). Passive systems are inherently less stable than active systems and the PCCS encountered the flashing-induced instability previously identified. The objective of this study is to develop stability maps for flashing-induced instability using MARS (Multi-dimensional Analysis of Reactor Safety) code. Firstly, we conducted a series of sensitivity analysis to see the effects of time step size, nodalization, and alternative MARS user options on the onset of flashing-induced instability. The riser nodalization strongly affects the prediction of flashing in a long riser of the PCCS, while time step size and alternative user options do not. Based on the sensitivity analysis, a standard input and an analysis methodology were set up to develop the stability maps of PCCS. We found out that the calculated equilibrium quality at the exit of the riser as a stability boundary above 5 kW/㎡ was approximately 1.2%, which was in good agreement with Furuya's results. However, in case of a very low heat flux condition, the onset of instability occurred at the lower equilibrium quality. In addition, it was confirmed that inlet throttling reduces the unstable region.

The K-Partition Flash Code with BIFC-based Sharing and some Variants

Riz Rupert L. Ortiz,Proceso L. Fernandez, Jr. 보안공학연구지원센터 2014 International Journal of Multimedia and Ubiquitous Vol.9 No.9

Quasi-Primitive Block-Wise Concatenated BCH Codes With Collaborative Decoding for NAND Flash Memories

Daesung Kim,Jeongseok Ha IEEE 2015 IEEE TRANSACTIONS ON COMMUNICATIONS Vol.63 No.10

<P>In this work, we propose a novel design rule of block-wise concatenated Bose-Chaudhuri-Hocquenghem (BC-BCH) codes for storage devices using multi-level per cell (MLC) NAND flash memories. BC-BCH codes designed in accordance with the proposed design rule are called quasi-primitive BC-BCH codes in which constituent BCH codes are deliberately chosen for their lengths to be as close to primitive BCH codes as possible. It will be shown that such quasi-primitive BC-BCH codes can achieve significant improvements of error-correcting capability over the existing BC-BCH codes when an iterative hard-decision based decoding (IHDD) is assumed. In addition, we propose a novel collaborative decoding algorithm which targets at resolving dominant error patterns associated with the IHDD. Error-rate performances of error-control systems with the proposed quasi-primitive BC-BCH and existing BC-BCH codes are compared. For more comprehensive performance comparisons, systems with a hypothetically long BCH code and a product code are also considered in the comparisons.</P>

An Aging Measurement Scheme for Flash Memory Using LDPC Decoding Information

Taegeun Kang(강태근),Hyunbean Yi(이현빈) 한국컴퓨터정보학회 2020 韓國컴퓨터情報學會論文誌 Vol.25 No.1

웨어-레벨링과 오류정정코드는 플래시 메모리의 신뢰성과 내구성을 위한 필수적인 기술이다. 플래시 메모리를 구성하는 요소들은 사용횟수에 따른 노화도가 서로 다를 수 있다. 따라서 기존의 쓰기/지우기 횟수를 바탕으로 하는 웨어-레벨링 기술은 요소들의 실제 노화도 차이를 반영하기에 충분하지 않다. 본 논문에서는 높은 오류정정율이 증명된 Low-Dencity Parity-Check (LDPC) 코드를 적용하고 복호 과정에서 나오는 정보를 이용하여 플래시 메모리의 실제 노화도를 측정하는 방법을 소개한다. 실험에서는 실제 플래시 메모리를 대상으로 측정한 오류율 데이터를 기반으로 LDPC 코드 복호 정보가 플래시 메모리 각 블록의 노화도를 나타낼 수 있음을 보인다. 또한, 웨어-레벨링 시뮬레이션을 통하여 제안하는 노화도 측정 방법 기반의 웨어-레벨링의 효과를 입증한다. Wear-leveling techniques and Error Correction Codes (ECCs) are essential for the improvement of the reliability and durability of flash memories. Low-Density Parity-Check (LDPC) codes have higher error correction capabilities than conventional ECCs and have been applied to various flash memory-based storage devices. Conventional wear-leveling schemes using only the number of Program/Erase (P/E) cycles are not enough to reflect the actual aging differences of flash memory components. This paper introduces an actual aging measurement scheme for flash memory wear-leveling using LDPC decoding information. Our analysis, using error-rates obtained from an flash memory module, shows that LDPC decoding information can represent the aging degree of each block. We also show the effectiveness of the wear-leveling based on the proposed scheme through wear-leveling simulation experiments.

Combining Flash Codes for Write Deficiency Reduction

Riz Rupert L. Ortiz,Herbert R. Esling,Proceso L. Fernandez 보안공학연구지원센터 2014 International Journal of Software Engineering and Vol.8 No.4

Writing on Dirty Flash Memory: Combating Inter-Cell Interference via Coding with Side Information

Yongjune Kim,Euiseok Hwang,B. V. K. Vijaya Kumar 한국통신학회 2022 Journal of communications and networks Vol.24 No.6

High-density flash memories suffer from inter-cell interference (ICI) which threatens the reliability of stored data. In order to cope with the ICI problem, we propose a channel coding scheme with channel state information of flash memories (i.e., side information of ICI). This side information is obtained before writing data into flash memories and incorporated during the encoding stage. We show that flash memories under ICI problem can be transformed into the model of memory with defective cells due to the unique asymmetry property between write (page write) and erase (block erase) operations. Then, the channel coding for memory with defective cells is employed to combat ICI. Simulation results support that the proposed scheme with the ICI side information can effectively improve the decoding failure probability.