에너지 생산이 가능한 무선 센서 네트워크에서 잔여 에너지 인지 듀티-사이클 스케줄링 기법

이성원(Sungwon Lee),유홍석(Hongseok Yoo),김동균(Dongkyun Kim) 한국통신학회 2014 韓國通信學會論文誌 Vol.39 No.10(네트워크)

네트워크 수명을 연장시키기 위해 무선 센서 네트워크에서는 idle listening에 소비되는 에너지를 줄일 수 있는 듀티-사이클 MAC 프로토콜들이 제안되었다. 일반적인 듀티-사이클 MAC 프로토콜에서 각 센서 노드는 잔여 에너지양을 기반으로 듀티-사이클 주기를 계산한다. 그러나 에너지 수집이 가능한 센서 네트워크에서 기존 듀티-사이클 주기는 에너지 수집률이 높은 센서 노드에 불필요한 sleep 지연을 발생시킨다. 따라서 우리는 이전 연구에서 잔여 에너지양과 에너지 수집률을 함께 고려하여 듀티 사이클-주기를 조절하는 듀티-사이클 스케줄링 기법을 제안하였다. 그러나 이러한 듀티-사이클 MAC 프로토콜들은 듀티 사이클-주기 변화에 따른 성능 차이를 고려하지 않고 듀티-사이클 주기를 항상 선형적으로 조절하므로, 응용의 요구사항에 맞는 최적의 듀티 사이클 주기를 얻지 못한다. 본 논문에서는 듀티-사이클 주기를 계산하는 세 가지 기법들을 제안하고 그 결과에 대해 분석한다. 실험을 통해 제안된 기법들이 기존 듀티-사이클 스케줄링 기법에 비해 네트워크 수명, 단대단 패킷 전송 시간과 패킷 전송률을 각각 최대 23%, 44%, 31% 증가시킴을 확인하였다. In order to increase network lifetime, duty-cycle MAC protocols which can reduce energy consumption caused by idle listening is proposed for WSNs. In common duty-cycle MAC protocols, each sensor node calculates its duty-cycle interval based on the current amount of residual energy. However, in WSNs with the capability of energy harvesting, existing duty-cycle intervals based on the residual energy may cause the sensor nodes which have high energy harvesting rate to suffer unnecessary sleep latency. Therefore, a duty-cycle scheduling scheme which adjust the duty-cycle interval based on both of the residual energy and the energy harvesting rate was proposed in our previous work. However, since this duty-cycle MAC protocol overlooked the performance variation according to the change of duty-cycle interval and adjusted the duty-cycle interval only linearly, the optimal duty-cycle interval could not be obtained to meet application requirements. In this paper, we propose three methods which calculate the duty-cycle interval and analyse their results. Through simulation study, we verify that network lifetime, end-to-end delay and packet delivery ratio can be improved up to 23%, 44% and 31% as compared to the existing linear duty-cycle scheduling method, respectively.

고속 DRAM을 위한 Duty Cycle 보정 기능을 가진 Analog Synchronous Mirror Delay 회로의 설계

최훈,김주성,장성진,이재구,전영현,공배선,Choi Hoon,Kim Joo-Seong,Jang Seong-Jin,Lee Jae-Goo,Jun Young-Hyun,Kong Bai-Sun 대한전자공학회 2005 電子工學會論文誌-SD (Semiconductor and devices) Vol.42 No.9

본 논문에서는 duty cycle-corrected analog synchronous mirror delay(DCC-ASMD)라고 불리는 새로운 구조의 내부 클럭 생성기를 제안한다. 제안된 회로는 임의의 duty ratio를 가진 외부 클럭에 대하여 duty ratio가 $50\%$로 보정된 내부 클럭을 2클럭 주기 만에 생성할 수 있다. 그러므로, 본 내부 클럭 생성기는 double data-rate (DDR) synchronous DRAM (SDRAM)과 같은 듀얼 에지 동기형 시스템(dual edge-triggered system)에 효율적으로 이용될 수 있다. 제안된 기술의 타당성을 평가하기 위하여, $0.35\mu$m CMOS 공정기술을 이용하여 제안된 내부 클럭 생성기를 구현하여 모사실험을 실행하였다. 실험 결과, 제안된 내부 클럭 생성기는, $40\~60$의 duty ratio를 갖는 외부 클럭 신호에 대하여, 50$\%$ duty ratio를 갖는 내부 클럭 신호를 2 클럭 주기 만에 발생시킬 수 있음을 확인하였다. This paper describes a novel internal clock generator, called duty cycle-corrected analog synchronous mirror delay (DCC-ASMD). The proposed circuit is well suited for dual edge-triggered systems such as double data-rate synchronous DRAM since it can achieve clock synchronization within two clock cycles with accurate duty cycle correction. To evaluate the performance of the proposed circuit, DCC-ASMD was designed using a $0.35\mu$m CMOS process technology. Simulation results show that the proposed circuit generates an internal clock having $50\%$ duty ratio within two clock cycles from the external clock having duty ratio range of $40\;\~\;60$.

3-3.5㎓ 대역폭 지원을 위한 오류 보상 듀티 주기 검출기를 구현한 듀티 주기 교정기

이민섭(MinSeop Lee),박현수(HyunSu Park),심진철(JinCheol Sim),권영욱,전진우(JinWoo Jeon),유정식(Jeongsik Yoo),박수호(SooHo Park),김철우(ChulWoo Kim) 대한전자공학회 2020 대한전자공학회 학술대회 Vol.2020 No.8

High-speed memory interface system such as double data rate(DDR) memories require an exact 50% duty cycle system clock for optimal valid data window. This paper presents a duty cycle corrector (DCC) using error compensate duty cycle detector(DCD). The proposed DCC consists of a DCD which implemented error detecting and correcting function, a duty-cycle adjuster, controller and output buffer. The proposed DCC circuit has been implemented and fabricated in a 28-nm CMOS process and occupies 2742<SUP>2</SUP>. The acceptable input clock frequency is from 3㎓ to 3.5㎓ and acceptable duty cycle variation is ±20%. The measured maximum duty-cycle error for the 50% duty-rate is 3.8%.

A 0.5-2.0 GHz Dual-Loop SAR-controlled Duty-Cycle Corrector Using a Mixed Search Algorithm

Han, Sangwoo,Kim, Jongsun The Institute of Electronics and Information Engin 2013 Journal of semiconductor technology and science Vol.13 No.2

This paper presents a fast-lock dual-loop successive approximation register-controlled duty-cycle corrector (SARDCC) circuit using a mixed (binary+sequential) search algorithm. A wider duty-cycle correction range, higher operating frequency, and higher duty-cycle correction accuracy have been achieved by utilizing the dual-loop architecture and the binary search SAR that achieves the fast duty-cycle correcting property. By transforming the binary search SAR into a sequential search counter after the first DCC lock-in, the proposed dual-loop SARDCC keeps the closed-loop characteristic and tracks variations in process, voltage, and temperature (PVT). The measured duty cycle error is less than ${\pm}0.86%$ for a wide input duty-cycle range of 15-85 % over a wide frequency range of 0.5-2.0 GHz. The proposed dual-loop SARDCC is fabricated in a 0.18-${\mu}m$, 1.8-V CMOS process and occupies an active area of $0.075mm^2$.

Reinforcement Learning-based Duty Cycle Interval Control in Wireless Sensor Networks

Shathee Akter,Seokhoon Yoon 한국인터넷방송통신학회 2018 International journal of advanced smart convergenc Vol.7 No.4

One of the distinct features of Wireless Sensor Networks (WSNs) is duty cycling mechanism, which is used to conserve energy and extend the network lifetime. Large duty cycle interval introduces lower energy consumption, meanwhile longer end-to-end (E2E) delay. In this paper, we introduce an energy consumption minimization problem for duty-cycled WSNs. We have applied Q-learning algorithm to obtain the maximum duty cycle interval which supports various delay requirements and given Delay Success ratio (DSR) i.e. the required probability of packets arriving at the sink before given delay bound. Our approach only requires sink to compute Q-leaning which makes it practical to implement. Nodes in the different group have the different duty cycle interval in our proposed method and nodes don’t need to know the information of the neighboring node. Performance metrics show that our proposed scheme outperforms existing algorithms in terms of energy efficiency while assuring the required delay bound and DSR.

A CMOS Duty Cycle Corrector Using Dynamic Frequency Scaling for Coarse and Fine Tuning Adjustment

Sangwoo Han(한상우),Jongsun Kim(김종선) 대한전자공학회 2012 전자공학회논문지 Vol.49 No.10

Unsynchronized Duty-cycle Control for Sensor Based Home Automation Networks

( Dongho Lee ),( Kwangsue Chung ) 한국인터넷정보학회 2012 KSII Transactions on Internet and Information Syst Vol.6 No.4

Home automation networks are good environments for merging sensor networks and consumer electronics technologies. It is very important to reduce the energy consumption of each sensor node because sensor nodes operate with limited power based on a battery that cannot be easily replaced. One of the primary mechanisms for achieving low energy operation in energy-constrained wireless sensor networks is the duty-cycle operation, but this operation has several problems. For example, unnecessary energy consumption occurs during synchronization between transmission schedules and sleep schedules. In addition, a low duty-cycle usually causes more performance degradation, if the network becomes congested. Therefore, an appropriate control scheme is required to solve these problems. In this paper, we propose UDC (Unsynchronized Duty-cycle Control), which prevents energy waste caused by unnecessary preamble transmission and avoids congestion using duty-cycle adjustment. In addition, the scheme adjusts the starting point of the duty-cycle in order to reduce sleep delay. Our simulation results show that UDC improves the reliability and energy efficiency while reducing the end-to-end delay of the unsynchronized duty-cycled MAC (Media Access Control) protocol in sensor-based home automation networks.

고속 SoC를 위한 클락 듀티 보정회로의 설계

한상우(Sang Woo Han),김종선(Jong Sun Kim) 한국산업정보학회 2013 한국산업정보학회논문지 Vol.18 No.5

본 논문에서는 고속 SoC 설계시 필요한 클록킹 회로의 핵심 소자인 클록 듀티 보정회로 (Duty-Cycle Corrector: DCC)를 소개한다. 종래의 아날로그 피드백 DCC와 디지털 피드백 DCC의 구조와 동작에 대해 비교 분석한다. 듀티-보정 레인지의 확장과 동작 주파수 및 듀티-보정 정확도의 향상을 위해 아날로그와 디지털 DCC의 장점을 결합한 새로운 혼성-모드 피드백 DCC를 소개한다. 특히, 혼성-모드 DCC의 핵심 구성 회로인 듀티-앰프 (Duty-Cycle Amplifier: DCA)의 구조와 설계에 대해 자세히 소개한다. 싱글-스테이지 DCA와 투-스테이지 DCA 기반의 두 개의 혼성-모드 DCC가 각각 0.18-㎛ CMOS 공정으로 설계되었고, 투-스테이지 DCA기반 DCC가 더 넓은 듀티-보정 레인지와 더 적은 듀티-보정 에러를 갖고 있음을 증명하였다. A clock duty-cycle corrector (DCC) which is an essential device of clocking circuits for high-speed system-on-chip (SoC) design is introduced in this paper. The architectures and operation of conventional analog feedback DCCs and digital feedback DCCs are compared and analyzed. A new mixed-mode feedback DCC that combines the advantages of analog DCCs and digital DCCs to achieve a wider duty-cycle correction range, higher operating frequency, and higher duty-cycle correction accuracy is presented. Especially, the architectures and design of a mixed-mode duty-cycle amplifier (DCA) which is a core unit circuit of a mixed-mode DCC is presented in detail. Two mixed-mode DCCs based on a single-stage DCA and a two-stage DCA were designed in a 0.18-㎛ CMOS process, and it is proven that the two-stage DCA-based DCC has a wider duty-cycler correction range and smaller duty-cycle correction error.

신경회로망을 이용한 에어컨의 가변주기제어 방법론 개발

金亨中(Hyeong-Jung Kim),杜錫培(Seog-Bae Doo),朴宗培(Jong-Bae Park),愼重麟(Joong-Rin Shin) 대한전기학회 2006 전기학회논문지A Vol.55 No.10

This paper presents a novel method for satisfying the thermal comfort of indoor environment and reducing the summer peak demand power by minimizing the power consumption for an Air-conditioner within a space. Korea Electric Power Corporation (KEPCO) use the fixed duty cycle control method regardless of the indoor thermal environment. However, this method has disadvantages that energy saving depends on the set-point value of the Air-Conditioner and direct load control (DLC) has no net effects on Air-conditioners if the appliance has a lower operating cycle than the fixed duty cycle. In this paper, the variable duty cycle control method is proposed in order to compensate the weakness of conventional fixed duty cycle control method and improve the satisfaction of residents and the reduction of peak demand. The proposed method estimates the predict mean vote (PMV) at the next step with predicted temperature and humidity using the back propagation neural network model. It is possible to reduce the energy consumption by maintaining the Air-conditioner's OFF state when the PMV lies in the thermal comfort range. To verify the effectiveness of the proposed variable duty cycle control method, the case study is performed using the historical data on Sep, 7th, 2001 acquired at a classroom in Seoul and the obtained results are compared with the fixed duty cycle control method.

MDA-SMAC: An Energy-Efficient Improved SMAC Protocol for Wireless Sensor Networks

( Xu Donghong ),( Wang Ke ) 한국인터넷정보학회 2018 KSII Transactions on Internet and Information Syst Vol.12 No.10

In sensor medium access control (SMAC) protocol, sensor nodes can only access the channel in the scheduling and listening period. However, this fixed working method may generate data latency and high conflict. To solve those problems, scheduling duty in the original SMAC protocol is divided into multiple small scheduling duties (micro duty MD). By applying different micro-dispersed contention channel, sensor nodes can reduce the collision probability of the data and thereby save energy. Based on the given micro-duty, this paper presents an adaptive duty cycle (DC) and back-off algorithm, aiming at detecting the fixed duty cycle in SMAC protocol. According to the given buffer queue length, sensor nodes dynamically change the duty cycle. In the context of low duty cycle and low flow, fair binary exponential back-off (F-BEB) algorithm is applied to reduce data latency. In the context of high duty cycle and high flow, capture avoidance binary exponential back-off (CA-BEB) algorithm is used to further reduce the conflict probability for saving energy consumption. Based on the above two contexts, we propose an improved SMAC protocol, micro duty adaptive SMAC protocol (MDA-SMAC). Comparing the performance between MDA-SMAC protocol and SMAC protocol on the NS-2 simulation platform, the results show that, MDA-SMAC protocol performs better in terms of energy consumption, latency and effective throughput than SMAC protocol, especially in the condition of more crowded network traffic and more sensor nodes.