Delta-bar-Delta 알고리즘을 이용한 ODVS의 좌표 교정

김도현,박용민,차의영,Kim Do-Hyeon,Park Young-Min,Cha Eui-Young 한국정보통신학회 2005 한국정보통신학회논문지 Vol.9 No.3

본 논문에서는 카타디옵트릭 카메라로부터 획득한 전 방향 구면 왜곡 영상에서의 좌표를 실제 거리좌표로 변환하기 위해서 3차원 포물면 좌표 변환 방법과 Delta-bar-delta 알고리즘에 의한 좌표 교정방법을 제시하였다. 실험을 통해 살펴본 결과 제안된 좌표 변환 방법이 환경 변수에 민감한 좌표 변환에서의 정확성 및 신뢰성을 가짐을 알 수 있었다. This paper proposes coordinates transformation and calibration algorithm using 3D parabolic coordinate transformation and delta-bar-delta neural algorithm for the omni-directional image captured by catadioptric camera. Experimental results shows that the proposed algorithm has accuracy and confidence in coordinate transformation which is sensitive to environmental variables.

무선 센서 네트워크상에서 코드뱅킹 및 델타이미지 기반의 효율적인 센서노드 소프트웨어 업데이트 기법

남영진,남민석,박영균,김창훈,이동하,Nam, Young-Jin,Nam, Min-Seok,Park, Young-Kyun,Kim, Chang-Hoon,Lee, Dong-Ha 대한임베디드공학회 2009 대한임베디드공학회논문지 Vol.4 No.3

Software update has been regarded as one of fundamental functions in wireless sensor networks. It can disseminate a delta-image between a current software image operating on a sensor node and its new image in order to reduce an update image(transmission data) size, resultantly saving energy. In addition, code-banking capability of micro-controllers can decrease the update image size. In order to maximize the efficiency of the software update, the proposed scheme exploits both the delta-image and the code-banking at the same time. Besides, it additionally delivers a recovery delta-image to properly handle abnormal conditions, such as message corruptions and unexpected power-off during the update.

A Low-power Extended-counting Delta-sigma ADC for CMOS Image Sensors

Woo-Tae Kim,Byung-geun Lee 대한전자공학회 2019 Journal of semiconductor technology and science Vol.19 No.6

This paper presents an incremental delta sigma analog to digital converter (ADC) using an extended counting technique for CMOS image sensors. A modified extended counting method is proposed to reduce the over sampling ratio (OSR) and consequently increase conversion speed without increasing the hardware complexity. To further reduce the chip size and power consumption, a self-biased amplifier is shared between the adjacent stages of the delta-sigma modulator. The proposed ADC is fabricated in a 0.18-µm CMOS image sensor process and occupies 0.0026 mm2. It achieves 65 dB of signal noise and distortion ratio (SNDR) for a signal bandwidth of 156.25 kHz with a 20 MHz operating clock and consumes 45 µW from a 1.8 V power supply. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.49 / −0.22 and +0.61 / −0.64 LSB (least significant byte), respectively.

A Single-Bit 2nd-Order Delta-Sigma Modulator with 10-μm Column-Pitch for a Low Noise CMOS Image Sensor

Min-Woo Kwon(권민우),Jimin Cheon(천지민) 한국정보전자통신기술학회 2020 한국정보전자통신기술학회논문지 Vol.13 No.1

본 논문에서는 polymerase chain reaction (PCR) 응용에 적합한 저잡음 CMOS 이미지 센서에 사용되는 컬럼-패러럴 analog-to-digital converter (ADC) 어레이를 위한 cascaded-of-integrator feedforward (CIFF) 구조의 단일 비트 2차 델타-시그마 모듈레이터를 제안하였다. 제안된 모듈레이터는 CMOS 이미지 센서에 입사된 빛의 신호에 해당하는 픽셀 출력 전압을 디지털 신호로 변환시키는 컬럼-패러럴 ADC 어레이를 위해 하나의 픽셀 폭과 동일한 10μm 컬럼 폭 내에 2개의 스위치드 커패시터 적분기와 단일 비트 비교기로 구현하였다. 또한, 모든 컬럼의 모듈레이터를 동시에 구동하기 위한 주변 회로인 비중첩 클록 발생기 및 바이어스 회로를 구성하였다. 제안된 델타-시그마 모듈레이터는 110nm CMOS 공정으로 구현하였으며 12kHz 대역폭에 대해 418의 oversampling ratio (OSR)로 88.1dB의 signal-to-noise-and-distortion ratio (SNDR), 88.6dB의 spurious-free dynamic range (SFDR) 및 14.3비트의 effective-number-of-bits (ENOB)을 달성하였다. 델타 시그마 모듈레이터의 면적 및 전력 소비는 각각 970⨯10 μ㎡ 및 248μW이다. In this paper, a single-bit 2nd-order delta-sigma modulator with the architecture of cascaded-of-integrator feedforward (CIFF) is proposed for column-parallel analog-to-digital converter (ADC) array used in a low noise CMOS image sensor. The proposed modulator implements two switched capacitor integrators and a single-bit comparator within only 10-μm column-pitch for column-parallel ADC array. Also, peripheral circuits for driving all column modulators include a non-overlapping clock generator and a bias circuit. The proposed delta-sigma modulator has been implemented in a 110-nm CMOS process. It achieves 88.1-dB signal-to-noise-and-distortion ratio (SNDR), 88.6-dB spurious-free dynamic range (SFDR), and 14.3-bit effective-number-of-bits (ENOB) with an oversampling ratio (OSR) of 418 for 12-kHz bandwidth. The area and power consumption of the delta-sigma modulator are 970⨯10 μ㎡ and 248 μW, respectively.

A Low-Noise and Area-Efficient PWM- <tex> $\Delta \Sigma $</tex> ADC Using a Single-Slope Quantizer for CMOS Image Sensors

Yun-Rae Jo,Seong-Kwan Hong,Oh-Kyong Kwon Institute of Electrical and Electronics Engineers 2016 IEEE transactions on electron devices Vol.63 No.1

<P>This paper proposes a multibit pulsewidth modulated (PWM) delta-sigma (Delta Sigma) analog-to-digital converter (ADC) using a single-slope (SS) quantizer for a CMOS image sensor (CIS). In the proposed ADC, the multibit Delta Sigma modulation is performed by converting the pulsewidth of the PWM signal into multibit data using an SS quantizer. This suppresses the random noise by the multisampling operation and reduces the area of the multibit Delta Sigma ADC by adding a ramp signal to a single-bit Delta Sigma ADC. The proposed ADC with 12-b resolution was fabricated using a 0.13-mu m CIS process with a pixel array which has a Bayer patterned color filter and an image format of 580 x 450 with a pixel size of 5 mu m x 5 mu m. The size of the test chip is 4 mm x 5 mm, including the area of the proposed channel ADC, which occupies only 10 mu m x 400 mu m per channel. The measured results show a random noise of 65 mu V and a dynamic range of 70.4 dB.</P>

New Algorithm in the Particle Tracking Velocimetry using Self-Organizing Map

Joshi Shashidhar Ram 한국멀티미디어학회 2010 한국멀티미디어학회 국제학술대회 Vol.2010 No.-

The self-organizing maps (SOM) model seems to have turned out particularly effective for the particle tracking algorithm of the PIV system. This is mainly because of the performance of the particle tracking itself, capacity of dealing with unpaired particles between two frames and no necessity for a priori knowledge on the flow field (e.g. maximum flow rate) to be measured. Initially, concept of SOM was applied to PIV by Labonte. It was modified by Ohmi and further modified algorithm is developed using the concept of Delta-Dar-Delta rule. It is a heuristic algorithm for modifying the learning rate as training progresses. Earlier, the treatment of unpaired particles, a specific problem to any type of PIV, is not fully considered and thereby, the tracking goes unsuccessfully for some particles. The present research is to bring about further improvement and practicability in this promising particle tracking algorithm. The computational complexity can be reduced employing modified algorithm compared to other algorithms. The modified algorithm is tested in the light of the synthetic PIV standard image as well as in particle images obtained from visualization experiments.

A Low-power Incremental Delta-sigma ADC with Adaptive Biasing for CMOS Image Sensors

Dong-Hwan Seo,Jung-Gyun Kim,Byung-Geun Lee 대한전자공학회 2023 Journal of semiconductor technology and science Vol.23 No.5

This paper presents the design and fabrication of a low-power incremental delta-sigma analog-to-digital converter (ADC) with an adaptive bias technique suitable for complimentary metal-oxide semiconductor (CMOS) image sensors (CISs). The adaptive biasing circuitry provides the amplifier with a predicted minimum current value required for the integrator output to settle; this optimized current flows through the amplifier and reduces power consumption by 40%. A prototype ADC fabricated using a 0.18 µm CMOS process, achieves an SNDR of 65 dB at a sampling frequency of 25 MHz and consumes 13.5 µW from a 1.8 V power supply. The measured differential and integral nonlinearities are +0.31/-0.42 and +0.62/-0.75 at a 12-bit accuracy, respectively.

영상처리를 적용한 90⁰ 델타로봇의 제어시스템

이하나(Ha-Na Lee),김기태(Gi-Tea Kim),정광현(Kwang-Hyeon Chung),차동혁(Dong-Hyuk Cha),정명진(Myung-Jin Chung) 대한기계학회 2021 대한기계학회 춘추학술대회 Vol.2021 No.11

In this study, we propose an image processing position control system for 90-degree delta robot with four actuators. The robot places four actuators arranged at 90-degree to solve the problem of overloading the motor of the conventional 120 degrees delta robot. Inverse kinematics was used to move the delta robot in its exact location. Image processing can be used to control the position of the end effector of the delta robot. For image processing, position of the webcam at a 70-degree angle at 32cm height. The system allows us to determine the position, color, and slope of shapes. The measuring area is 30cm wide and 20cm long. The area that can be driven by image processing is the same as the measurement area. The operation of the proposed delta robot was confirmed, and the operation experiment was carried out.

Delta Robot and Image Processing

Truong Xuan Phat,Tran Trung Nghia 제어로봇시스템학회 2020 제어로봇시스템학회 국제학술대회 논문집 Vol.2020 No.10

In many industrial chain, picking, ordering and sorting object are difficult task for human to deal with. They require accuracy, vision analyzing and quick response. There for, Delta Robot application is suitable for its specification. A typical application is picking task which require speed and accuracy, classify goods such as candy bars into boxes. Furthermore, a camera is used to identify the given object, return the position of that object to the robot. This combination is rather effective, accurate and adjustable than the traditional ways which is using human labor. These can be achieved by studies of Delta Robot Kinematic for controlling as well as image processing algorithm developing. The research also identifies the working space and applied mathematic.

Low-Power CMOS image sensor with multi-column-parallel SAR ADC

( Jang-Su Hyun ),( Hyeon-june Kim ) 한국센서학회 2021 센서학회지 Vol.30 No.4

This work presents a low-power CMOS image sensor (CIS) with a multi-column-parallel (MCP) readout structure while focusing on improving its performance compared to previous works. A delta readout scheme that utilizes the image characteristics is optimized for the MCP readout structure. By simply alternating the MCP readout direction for each row selection, additional memory for the rowto- row delta readout is not required, resulting in a reduced area of occupation compared to the previous work. In addition, the bias current of a pre-amplifier in a successive approximate register (SAR) analog-to-digital converter (ADC) changes according to the operating period to improve the power efficiency. The prototype CIS chip was fabricated using a 0.18-μm CMOS process. A 160 × 120 pixel array with 4.4 μm pitch was implemented with a 10-bit SAR ADC. The prototype CIS demonstrated a frame rate of 120 fps with a total power consumption of 1.92mW.