12-비트 10-MS/s CMOS 파이프라인 아날로그-디지털 변환기

조세현(Se-Hyeon Cho),정호용(Ho-yong Jung),도원규(Won-Kyu Do),이한열(Han-Yeol Lee),장영찬(Young-Chan Jang) 한국전기전자학회 2021 전기전자학회논문지 Vol.25 No.2

본 논문에서는 영상 처리용 12-비트의 10-MS/s 파이프라인 아날로그-디지털 변환기(ADC: analog-to-digital converter)가 제안된다. 제안된 ADC는 샘플-홀드 증폭기, 3개의 stage, 3-비트 플래시 ADC, 그리고 digital error corrector로 구성된다. 각 stage는 4-비트 flash ADC와 multiplying digital-to-analog ADC로 구성된다. 고해상도의 ADC를 위해 제안된 샘플-홀드 증폭기는 gain boosting을 이용하여 전압 이득을 증가시킨다. 제안된 파이프라인 ADC는 1.8V 공급전압을 사용하는 180㎚ CMOS 공정에서 설계되었고 차동 1V 전압을 가지는 1㎒ 사인파 아날로그 입력신호에 대해 10.52-비트의 유효 비트를 가진다. 또한, 약 5㎒의 나이퀴스트 사인파 입력에 대해 측정된 유효비트는 10.12 비트이다. A 12-bit 10-MS/s pipeline analog-to-digital converter (ADC) is proposed for image processing applications. The proposed pipeline ADC consists of a sample and hold amplifier, three stages, a 3-bit flash analog-to-digital converter, and a digital error corrector. Each stage is operated by using a 4-bit flash ADC (FADC) and a multiplying digital-to-analog converter (MDAC). The proposed sample and hold amplifier increases the voltage gain using gain boosting for the ADC with high resolution. The proposed pipelined ADC is designed using a 180-㎚ CMOS process with a supply voltage of 1.8 and it has an effective number of bit (ENOB) of 10.52 bits at sampling rate of 10MS/s for a 1-Vpp differential sinusoidal analog input with frequency of 1 ㎒. The measured ENOB is 10.12 bits when the frequency of the sinusoidal analog input signal is a Nyquist frequency of approximately 5 ㎒.

TMS320F28377D 기반 아날로그-디지털 신호 처리 시스템

최준영,김형우,남기곤 대한임베디드공학회 2019 대한임베디드공학회논문지 Vol.14 No.1

We propose an embedded solution to design a high-speed and high-accuracy 16bit analog-digital signal processing interface for the control systems using various external analog signals. Choosing TMS320F28377D micro controller unit (MCU) featuring high-performance processing in the 32-bit floating point operation, low power consumption, and various I/O device supports, we design and build the proposed system that supports both 16-bit analog-digital converter (ADC) interface and high precision digital-analog converter (DAC) interface. The ADC receives voltage-level differential signals from fully differential amplifiers, and the DAC communicates with MCU through 50 MHz bandwidth high-fast serial peripheral interface (SPI). We port the boot loader and device drivers to the implemented board, and construct the firmware development environment for the application programming. The performance of the entire implemented system is demonstrated by analog-digital signal processing tests, and is verified by comparing the test results with those of existing similar systems.

단일-극 커패시터 방식의 터치센서를 위한 Incremental 델타-시그마 아날로그-디지털 변환기 설계

정영재,노정진,Jung, Young-Jae,Roh, Jeong-Jin 한국전기전자학회 2013 전기전자학회논문지 Vol.17 No.3

본 논문에서는 단일-극 커패시터 방식의 터치센서를 위한 incremental 델타-시그마 아날로그-디지털 변환기를 설계하였다. 델타-시그마 모듈레이터의 구조는 단일비트 2차 cascade of integrators with distributed feedback(CIFB)를 사용하였으며 $0.18-{\mu}m$ CMOS 공정을 이용하여 제작하였다. Incremental 델타-시그마 아날로그-디지털 변환기의 입력으로 이어지는 센서가 넓은 입력 범위를 얻고 높은 정확성을 가지도록 변환기 앞에 shielding 신호와 디지털적으로 조절 가능한 오프-셋 커패시터를 위치시켰다. 본회로의 공급전압은 2.6 V에서 3.7 V이며 ${\pm}10-pF$의 입력범위를 가지고 fF 이하의 해상도를 필요로 하는 단일-극 커패시터 방식의 터치센서에 적합하다. This paper presents an incremental delta-sigma analog-to-digital converter (ADC) for a single-electrode capacitive touch sensor. The second-order cascade of integrators with distributed feedback (CIFB) delta-sigma modulator with 1-bit quantization was fabricated by a $0.18-{\mu}m$ CMOS process. In order to achieve a wide input range in this incremental delta-sigma analog-to-digital converter, the shielding signal and the digitally controlled offset capacitors are used in front of a converter. This circuit operated at a supply voltage of 2.6 V to 3.7 V, and is suitable for single-electrode capacitive touch sensor for ${\pm}10-pF$ input range with sub-fF resolution.

Expandable Flash-Type CMOS Analog-to-Digital Converter for Sensor Signal Processing

오창우,최병수,김진태,서상호,신장규,최평 한국센서학회 2017 센서학회지 Vol.26 No.3

The analog-to-digital converter (ADC) is an important component in various fields of sensor signal processing. This paper presents an expandable flash analog-to-digital converter (E-flash ADC) for sensor signal processing using a comparator, a subtractor, and a mul-tiplexer (MUX). The E-flash ADC was simulated and designed in 0.35-µm standard complementary metal-oxide semiconductor(CMOS) technology. For operating the E-flash ADC, input voltage is supplied to the inputs of the comparator and subtractor. When the input voltage is lower than the reference voltage, it is outputted through the MUX in its original form. When it is higher than the reference voltage, the reference voltage is subtracted from the input value and the resulting voltage is outputted through the MUX. Operation of the MUX is determined by the output of the comparator. Further, the output of the comparator is a digital code. The E-flash ADC can be expanded easily.

ADC-Based Backplane Receivers

Hayun Chung 대한전자공학회 2016 Journal of semiconductor technology and science Vol.16 No.3

The analog-to-digital-converter-based (ADCbased) backplane receivers that consist of a front-end ADC followed by a digital equalizer are gaining more popularity in recent years, as they support more sophisticated equalization required for high data rates, scale better with fabrication technology, and are more immune to PVT variations. Unfortunately, designing an ADC-based receiver that meets tight power and performance budgets of high-speed backplane link systems is non-trivial as both frontend ADC and digital equalizer can be power consuming and complex when running at high speed. This paper reviews the state of art designs for the front-end ADC and digital equalizers to suggest implementation choices that can achieve high speed while maintaining low power consumption and complexity. Design-space exploration using system-level models of the ADC-based receiver allows through analysis on the impact of design parameters, providing useful information in optimizing the power and performance of the receiver at the early stage of design. The system-level simulation results with newer device parameters reveal that, although the power consumption of the ADC-based receiver may not comparable to the receivers with analog equalizers yet, they will become more attractive as the fabrication technology continues to scale as power consumption of digital equalizer scales well with process.

An 11-bit 160-MS/s Non-binary C-based SAR ADC with a Partially Monotonic Switching Scheme

Jae-Hyuk Lee,Jun-Ho Boo,Jun-Sang Park,Tai-Ji An,Hee-Wook Shin,Young-Jae Cho,Michael Choi,Jin-Wook Burm,Gil-Cho Ahn,Seung-Hoon Lee 대한전자공학회 2023 Journal of semiconductor technology and science Vol.23 No.2

This work proposes a single-channel 11-bit successive-approximation register (SAR) analog-to-digital converter (ADC) with an operating speed of 160-MS/s based on a non-binary digital-to-analog converter (DAC) for settling error correction. In the proposed DAC, a non-binary-weighted structure with redundancy is employed for the upper 8-bit capacitor array to reduce the residual voltage settling time requirement, facilitating high-speed operation. The remaining 3-bit capacitor array is composed of three unit capacitors, which are attached to the fractional reference voltages generated from a resistor string (R-string). The proposed partially monotonic switching scheme reduces the switching power consumption and the common-mode voltage variations of the DAC output voltage. The proposed 3D-encapsulated capacitor layout reduces the interference of adjacent signals while securing the high linearity of capacitors. Implemented in a 28 nm CMOS, the proposed ADC consumes 1.67 mW of power with a 1.0 V supply voltage and occupies an active area of 0.026 mm2. The prototype ADC achieves a signal-to-noise-and-distortion-ratio (SNDR) and a spurious-free-dynamic-range (SFDR) of 53.5 dB and 67.5 dB, with a 9 MHz input at 160 MS/s, respectively.

A Gray-code Algorithmic Analog-to-Digital Converter based on Operational Conveyors

Wandee Petchmaneelumka,Amphawan Julsereewong 제어로봇시스템학회 2010 제어로봇시스템학회 국제학술대회 논문집 Vol.2010 No.10

This paper presents one-bit cell supporting input voltage to synthesize triangular-like DC transfer characteristic and digital output of Gray-code algorithmic analog-to-digital converter. The proposed one-bit cell is based on the use of operational conveyors in connection with resistors, diodes, and voltage comparator. An N-bit resolution can be simply realized by cascading the N proposed one-bit cells. Surpassing the previous one-bit cells using operational transconductance amplifiers, the proposed converter affords higher resolution and simpler configuration. The circuit operations of the proposed converter are confirmed through PSPICE simulation and experimental results.

센서 기반 헤모글로빈의 산소 포화도 측정을 위한 아날로그 프런트 엔드 설계 기술 및 방법

박세진,이호규,박종선,김철우,Park, Sejin,Lee, Hokyu,Park, Jongsun,Kim, Chulwoo 한국전기전자학회 2014 전기전자학회논문지 Vol.18 No.1

이 논문은 산소 포화도 측정을 위하여 설계되는 아날로그 프런트 엔드의 설계 기술 및 디자인 방법에 관한 것이다. 센서로부터 출력되는 데이터를 이용하여 산소포화도를 계산하기 위해서는 센서의 포토다이오드에서 흘려주는 전류 데이터를 전압 데이터로 바꿔주는 것이 필요하다. 설계된 아날로그 프런트 엔드는 센서로부터 출력되는 전류 데이터를 여러 가지 전압 이득을 가지는 형태로 후방의 아날로그 디지털 변환기에 전압을 전달하는 역할을 한다. 설계된 회로는 $0.11{\mu}m$ CMOS공정을 이용하여 설계되었으며, $0.174mm^2$의 면적을 차지한다. This paper describes the design technique and the method of analog front-end to measure the saturation of hemoglobin with oxygen sensor. To process the $SpO_2$ value from the sensor, the current data from the sensor should be converted into voltage domain. Designed analog front-end usually converts the current data from the sensor into voltage domain data to pass it on analog-to-digital converter called ADC with a different level of gain characteristics. This circuit was fabricated in a $0.11{\mu}m$ CMOS technology and has 4 level of gain properties. The occupied area is $0.174mm^2$.

고 방사선 환경을 위한 상용 디지털-아날로그 컨버터의 감마선 조사 시험 결과 및 분석

권인용 (사)한국방사선산업학회 2019 방사선산업학회지 Vol.13 No.1

This work presents irradiation test results of a commercial digital-to-analog converter(DAC) which is an essential component widely used in circuits and systems to convert naturalsignals from digital bits. Especially, a DAC requires a radiation tolerance in nuclear applications,for instance a nuclear black box which can store and transfer necessary data observed the statusof nuclear reactors in accident situations like Fukushima. The selected DAC is AD5433 of 10-bit and 10 MHz for multipurpose applications such as waveform generators, analog processing,instruments, programmable amplifiers and attenuators, digitally controlled calibration, compositevideo, and ultrasound. The test PCB includes two design-under-test (DUT) DACs controlled by amicrocontroller communicating with a PC. We observed the DUTs for 21 hours in the facility of highgamma energy irradiation at KAERI. The 10 V DAC outputs reached 3% of an allowable error after51 and 48 mins at the irradiation dose of 846 and 825 Gy, respectively. In the environment of severeaccidents, electrical components for observing reactor behaviors should be survived up to 5 kGyin total ionizing dose for approximately 72 hours that is minimum time to mitigate the accidentalsituation as soon as possible. However, the DACs were operated under 1 kGy, that is, we need abetter DAC specialized for the nuclear applications required such harsh environments.

A CMOS 5-bit 5GSample/Sec Analog-to-digital Converter in 0.13um CMOS

Wang, I-Hsin,Liu, Shen-Iuan The Institute of Electronics and Information Engin 2007 Journal of semiconductor technology and science Vol.7 No.1

This paper presents a high-speed flash analog-to-digital converter (ADC) for ultra wide band (UWB) receivers. In this flash ADC, the interpolating technique is adopted to reduce the number of the amplifiers and a linear and wide-bandwidth interpolating amplifier is presented. For this ADC, the transistor size for the cascaded stages is inversely scaled to improve the trade-off in bandwidth and power consumption. The active inductor peaking technique is also employed in the pre-amplifiers of comparators and the track-and-hold circuit to enhance the bandwidth. Furthermore, a digital-to-analog converter (DAC) is embedded for the sake of measurements. This chip has been fabricated in $0.13{\mu}m$ 1P8M CMOS process and the total power consumption is 113mW with 1V supply voltage. The ADC achieves 4-bit effective number of bits (ENOB) for input signal of 200MHz at 5-GSample/sec.