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CCN4 Regulates Vascular Smooth Muscle Cell Migration and Proliferation
Hao Liu,Zhengjun Liu,Wenpeng Dong,Zhiqi Lin,Jingbo Lu,Heng Wan,Zhongxin Zhou 한국분자세포생물학회 2013 Molecules and cells Vol.36 No.2
The migration and proliferation of vascular smooth muscle cells (VSMCs) are essential elements during the development of atherosclerosis and restenosis. An increasing number of studies have reported that extracellular matrix (ECM) proteins, including the CCN protein family, play a significant role in VSMC migration and proliferation. CCN4 is a member of the CCN protein family, which controls cell development and survival in multiple systems of the body. Here, we sought to determine whether CCN4 is involved in VSMC migration and proliferation. We examined the effect of CCN4 using rat cultured VSMCs. In cultured VSMCs, CCN4 stimulated the adhesion and migration of VSMCs in a dose-dependent manner, and this effect was blocked by an antibody for integrin 51. CCN4 expression was en-hanced by the pro-inflammatory cytokine tumor necrosis factor (TNF-). Furthermore, knockdown of CCN4 by siRNA significantly inhibited the VSMC proliferation. CCN4 also could up-regulate the expression level of marker proteins of the VSMCs phenotype. Taken together, these results suggest that CCN4 is involved in the migration and proliferation of VSMCs. Inhibition of CCN4 may provide a promising strategy for the prevention of restenosis after vascular interventions.
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Rongjun Chen,Yongrong Liao,Shengbin Liu,Yunyun Jiang,Changqiong Hu,Xuewei Zhang,Xufeng Cao,Zhengjun Xu,Xiaoling Gao,Lihua Li,Jianqing Zhu 한국유전학회 2017 Genes & Genomics Vol.39 No.1
Dirigent (DIR) and DIR-like family genes were involved in lignification or in the response to pathogen infection and abiotic stress in plants. Little is known to us about how rice DIR genes respond to adverse conditions. In this study, we reported genome-wide analysis of 49 DIR or DIR-likes genes in rice. The 49 OsDIRs or OsDIR-likes were tandem arranged into ten clusters. The phylogenetic analysis indicated that the 49 rice DIR and DIR-like genes cluster into five distinct subfamilies, DIR-a and four DIRlike subfamilies (DIR-b/d, and DIR-g, DIR-c, DIR-e). Meta-analysis of microarray gene expression datas indicated that all the OsDIRs or OsDIR-likes were expressed almost at the same level but with different patterns: most OsDIRs or OsDIR-likes were expressed exclusively in stigma and ovary and were induced by IAA and BAP; several genes were induced by trans-zeatin (tZ) and DMSO; 23 OsDIRs or OsDIR-likes were responded to abiotic stress. Our analysis also showed that most of these genes could respond to abiotic stresses, which contained cis-regulatory elements. The present study will provide a useful reference for further functional analysis of the DIR genes in rice.
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Multi-channel 5Gb/s/ch SERDES with Emphasis on Integrated Novel Clocking Strategies
Changchun Zhang,Ming Li,Zhigong Wang,Kuiying Yin,Qing Deng,Yufeng Guo,Zhengjun Cao,Leilei Liu 대한전자공학회 2013 Journal of semiconductor technology and science Vol.13 No.4
Two novel clocking strategies for a high-speed multi-channel serializer-deserializer (SERDES) are proposed in this paper. Both of the clocking strategies are based on groups, which facilitate flexibility and expansibility of the SERDES. One clocking strategy is applicable to moderate parallel I/O cases, such as high density, short distance, consistent media, high temperature variation, which is used for the serializer array. Each group within the strategy consists of full-rate phase-locked loop (PLL), a full-rate delay-locked loop (DLL), and t재 fixed phase alignment (FPA) techniques. The other is applicable to more awful I/O cases such as higher speed, longer distance, inconsistent media, serious crosstalk, which is used for the deserializer array. Each group within the strategy is composed of a PLL and two DLLs. Moreover, a half-rate version is chosen to realize the desired function of 1:2 deserializer. Based on the proposed clocking strategies, two representative ICs for each group of SERDES are designed and fabricated in a standard 0.18㎛ CMOS technology. Measurement results indicate that the two SERDES ICs can work properly accompanied with their corresponding clocking strategies.
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Jin Yong,Wang Zhilin,Zhang Zhenxin,Lin Bo,Ge Zhengjun,You Qidong,Chen Hao,Liu Xiliang,Xu Chenghao,Gao Shuaiqiang,Wu Yi,Abro Zafar 한국자원공학회 2023 Geosystem engineering Vol.26 No.4
CO2 flooding is a significant technology for oil recovery, to reveal the microcosmic mechanism of CO2 flooding, CO2 slim tube experiments, long core CO2 flooding experiments, gas chromatography analysis experiments, and numerical simulations were carried out. The results show that the miscibility increase can improve the effect of dissolution and diffusion in the CO2-crude oil system, easing the CO2 finger entry phenomena, and delaying gas breakthrough time. Besides, the CO2 -crude oil interaction is enhanced by increasing the pressure difference between the injection well and the production well, which improves the oil recovery of CO2 flooding. Besides, CO2 carries the light and medium components (C4 ~ 25) forward to cross the first miscible zone, which makes the CO2-crude oil system form double miscible zones. This study reveals the rule of CO2 front and light components front under different miscibility degrees of CO2 flooding from the microscopic perspective and deepens the theory of CO2 flooding in low-permeability sandstone reservoirs.
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Multi-channel 5Gb/s/ch SERDES with Emphasis on Integrated Novel Clocking Strategies
Zhang, Changchun,Li, Ming,Wang, Zhigong,Yin, Kuiying,Deng, Qing,Guo, Yufeng,Cao, Zhengjun,Liu, Leilei The Institute of Electronics and Information Engin 2013 Journal of semiconductor technology and science Vol.13 No.4
Two novel clocking strategies for a high-speed multi-channel serializer-deserializer (SERDES) are proposed in this paper. Both of the clocking strategies are based on groups, which facilitate flexibility and expansibility of the SERDES. One clocking strategy is applicable to moderate parallel I/O cases, such as high density, short distance, consistent media, high temperature variation, which is used for the serializer array. Each group within the strategy consists of a full-rate phase-locked loop (PLL), a full-rate delay-locked loop (DLL), and two fixed phase alignment (FPA) techniques. The other is applicable to more awful I/O cases such as higher speed, longer distance, inconsistent media, serious crosstalk, which is used for the deserializer array. Each group within the strategy is composed of a PLL and two DLLs. Moreover, a half-rate version is chosen to realize the desired function of 1:2 deserializer. Based on the proposed clocking strategies, two representative ICs for each group of SERDES are designed and fabricated in a standard $0.18{\mu}m$ CMOS technology. Measurement results indicate that the two SERDES ICs can work properly accompanied with their corresponding clocking strategies.
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