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Side Slip Angle Based Control Threshold of Vehicle Stability Control System
Taeyoung Chung,Kyongsu Yi 대한기계학회 2005 JOURNAL OF MECHANICAL SCIENCE AND TECHNOLOGY Vol.19 No.4
Vehicle Stability Control (VSC) system prevents vehicle from spinning or drifting out mainly by braking intervention. Although a control threshold of conventional VSC is designed by vehicle characteristics and centered on average drivers, it can be a redundancy to expert drivers in critical driving conditions. In this study, a manual adaptation of VSC is investigated by changing the control threshold. A control threshold can be determined by phase plane analysis of side slip angle and angular velocity which is established with various vehicle speeds and steering angles. Since vehicle side slip angle is impossible to be obtained by commercially available sensors, a side slip angle is designed and evaluated with test results. By using the estimated value, phase plane analysis is applied to determine control threshold. To evaluate an effect of control threshold, we applied a 23-DOF vehicle nonlinear model with a vehicle planar motion model based sliding controller. Controller gains are tuned as the control threshold changed. A VSC with various control thresholds makes VSC more flexible with respect to individual driver characteristics.
Frame loss concealment for stereoscopic video plus depth sequences
Tae-Young Chung,Sanghoon Sull,Chang-Su Kim IEEE 2011 IEEE transactions on consumer electronics Vol.57 No.3
<P>In this work, an efficient frame loss concealment algorithm for stereoscopic video plus depth sequences is proposed. To conceal an erroneous left color frame, we extrapolate motion vectors for the temporal error concealment. To conceal a left depth frame, we exploit the motion vectors of the corresponding left color frame. To conceal a right color frame, we employ a 3D image warping technique to determine matching pixels between inter-views, and perform the reconstruction based on the similarities of the motion vectors and the intensity differences of matching pixels. Finally, to conceal a right depth frame, we use the motion vectors of the right color frame and the left color frame. Simulation results show that the proposed algorithm is more effective than conventional algorithms in recovering erroneous color and depth frames. Moreover, it is also demonstrated that the proposed algorithm can be used for efficient virtual view synthesis in error prone environments.</P>
Tae-Young Chung,Jae-Young Sim,Chang-Su Kim IEEE 2014 IEEE TRANSACTIONS ON IMAGE PROCESSING - Vol.23 No.8
<P>An efficient bit allocation algorithm based on a novel view synthesis distortion model is proposed for the rate-distortion optimized coding of multiview video plus depth sequences in this paper. We decompose an input frame into nonedge blocks and edge blocks. For each nonedge block, we linearly approximate its texture and disparity values, and derive a view synthesis distortion model, which quantifies the impacts of the texture and depth distortions on the qualities of synthesized virtual views. On the other hand, for each edge block, we use its texture and disparity gradients for the distortion model. In addition, we formulate a bit-rate allocation problem in terms of the quantization parameters for texture and depth data. By solving the problem, we can optimally divide a limited bit budget between the texture and depth data, in order to maximize the qualities of synthesized virtual views, as well as those of encoded real views. Experimental results demonstrate that the proposed algorithm yields the average PSNR gains of 1.98 and 2.04 dB in two-view and three-view scenarios, respectively, as compared with a benchmark conventional algorithm.</P>
A Wideband CMOS Noise-Canceling Low-Noise Amplifier With High Linearity
Taeyoung Chung,Hankyu Lee,Daechul Jeong,Jehyung Yoon,Bumman Kim THE INSTITUTE OF ELECTRICAL ENGINEERS 2015 Vol. No.
<P>This letter presents a wideband noise-canceling LNA focusing on canceling IMD2 and IMD3. By using a complementary CMOS parallel push-pull structure, the IMD2 is cancelled. The modified noise-canceling circuit properly suppresses the IMD3. Although the optimum canceling points for the noise and distortions are different, the noise figure is not degraded by the choice. The LNA implemented in a 65 nm CMOS process delivers an IIP2 of 25 dBm, an IIP3 of 5.5 dBm with a power gain of 13 dB and an noise figure of 2.1-3.5 dB in a frequency range from 0.1 to 1.6 GHz. The power consumption is 20.8 mW at 1.2 V and the chip area is only 0.014 mm<SUP>2</SUP>.</P>
Sang-HyeonLee,JaekyuLee,YongseokAhn,DaewonHa,GwanhyeobKoh,TaeyoungChung,KinamKim,HyungSooUh 한국물리학회 2002 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.40 No.4
If the tight electrical performance requirements of the cell transistors used in giga-bit density DRAM are to be met, the leakage currents through the junction and the transistor should be controlled very carefully. In this paper, we propose a novel cell transistor using LOcalized Channel and Field Implantation (LOCFI) for low-power, reliable operation in a giga-bit density DRAM and beyond. When a LOCFI cell transistor is used, the data retention time is greatly improved by virtue of the reduced cell leakage currents resulting from the suppressed ion implantation damage at the storage node.
Novel Cell Architecture for High Performance of 512-Mb DRAM with 0.12-㎛ Design Rule
JaegooLee,ChanghyunCho,JuyongLee,MinsangKim,JaekyuLee,SoohoShin,DonghwaKwak,KwanhyeobKoh,GitaeJeong,HongsikJeong,TaeyoungChung,KinamKim 한국물리학회 2002 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.41 No.4
In this research, the data retention time was investigated for a high-speed the 0.12-um, low power 512-Mb DRAM (Dynamic Random Access Memory) with 0.12 m design rule. As the technology generation of DRAM has been developed into sub-quarter micron region, the control of the junction leakage current at the storage node has become much more important due to the increased channel doping concentration. In order to obtain high-performance DRAM with the 0.12-m design rule, we propose a novel trench isolation (shallow trench isolation) using self-aligned local field implantation to improve the data retention-time characteristics and to minimize the narrow-width eect in the cell transistor. This scheme reduces both the cell junction leakage current and the capacitance by relaxing the abrupt junction prole at the source and the drain regions. The relaxed junction prole can reduce the electric eld strength of junction and, thus, improve the data retention-time characteristic of the DRAM. We also tried to cure the surface defect by using a gate dual spacer and downstream Si-treatment. A high capacitance is realized by the dual molded oxide capacitor process. This novel storage node structure gives the capacitor much better mechanical stability. With the novel cell architecture, dramatic increases in the data retention time and the device yield were obtained for a 512-Mb DRAM. The proposed cell architecture can be extended fairly well to future high-density DRAM in 0.10 m technology and beyond.