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Jong-Wan Jo,Khuram Shehzad,Deeksha Verma,Sung Jin Kim,Young-Woo Park,Kwan-Tae Kim,Sang-Yun Kim,YoungGun Pu,Young-Goo Yang,Keum Cheol Hwang,Dong-Hun Lee,Hyung-Moon Kim,Kang-Yoon Lee 대한전자공학회 2020 Journal of semiconductor technology and science Vol.20 No.4
This paper presents the design of a 5-channel receiver for ocean acoustic measurement in very noisy environments. When measuring distances in the ocean through sonar, the input signal level to the receiver can change drastically depending on the distance between the transmitter and objects. Thus, a receiver with low sensitivity and a wide dynamic range is proposed in this work. In order to minimize the Input-Referred (IR) noise for the high sensitivity of the receiver, a low noise pre-amplifier is proposed and implemented, ultimately achieving a noise of 29.6 nV/√Hz at 50 kHz. In addition, a Sigma-Delta Analog-to-Digital Converter (SD ADC) with variable sampling rates is proposed by using the clock splitting technique in the Sigma-Delta Modulator (SDM) core. In addition, the decimation factor of the digital filter placed after the SDM in the SD ADC can be controlled so as to reduce the power consumption. Through the use of these techniques in the SD ADC, we can implement reconfigurable sampling rates from 1.5 MS/s to 12.5 MS/s with low power consumption. In order to overcome the limitation of the number of pins for multi-channel application, a Parallel-to-Serial (P2S) interface is proposed and designed in the receiver. The 5-channel receiver in this paper is implemented in a 0.18 μm CMOS process and the die area is 14.44 mm2. The total power consumption of this chip under a supply voltage of 2.4 V is 46.8 mW. The measured sensitivity and dynamic range are -100 dBV and 100 dB, respectively. The measured SNDR at the output of the SD ADC is 82.02 dB when the input signal frequency and sampling frequency are 7 kHz and 6.25 Msps, respectively. The maximum phase error between five channels is measured to be 0.8 °.
A Comprehensive Review on High-efficiency RF-DC Converter for Energy Harvesting Applications
Muhammad Basim,Qurat ul Ain,Khuram Shehzad,Syed Adil Ali Shah,Azam Ali,ByeongGi Jang,YoungGun Pu,Joon-Mo Yoo,Kang-Yoon Lee 대한전자공학회 2022 Journal of semiconductor technology and science Vol.22 No.5
The design of radiofrequency energy harvesting (RFRH) circuit for wearable devices, wireless sensor networks, and IoT applications can be classified mainly into radio frequency to direct current (RF-DC) converter, a transmitter and receiver antenna, an impedance matching network, and a storage device or a load. By scavenging RF energy from the ambient environment, this developing technology allows low-power wireless devices to be self-sustaining and environment friendly. To eliminate the need for batteries, RFEH technology has become a dependable and promising alternative for extending the lifetime of power-constrained wireless networks. This paper mainly focused on the input and output power, Power conversion efficiency (PCE), and sensitivity. Due to the weak and limited signal strength of received RF power, high-efficiency state-of-the-art RF energy harvesters must be designed to provide sufficient DC supply voltage to wireless networks. We provide in-depth information on the system's parameters. Optimum efficiency and maximum output power are the main concerns of an RFEH system. Therefore, RF Energy harvesting system review, antenna design, impedance matching, and RF-DC converter are presented in this paper to provide a deep insight into the design of the RFEH system. This article may help in identifying new research in the field of RF Energy Harvesting.
Design of a low noise analog Front-End System for Sonar Signal Conditioning Receiver
조종완,김성진,Muhammad Riaz ur Rehman,Khuram Shehzad,박영우,YoungGun Pu,이동헌,김형문,이강윤 한국과학기술원 반도체설계교육센터 2020 IDEC Journal of Integrated Circuits and Systems Vol.6 No.1
This paper presents the design of a low noise analog front end system for sonar signal conditioning receiver with Parallel to Series Interface in very noisy environments. When measuring distances in the ocean through sonar, the input signal level to the receiver can change drastically depending on the distance between the transmitter and objects. Thus, a receiver with low sensitivity and a wide dynamic range is proposed in this work. In order to minimize the Input-Referred (IR) noise for the high sensitivity of the receiver, a low noise pre-amplifier is proposed and implemented, ultimately achieving a noise of 11 nV/√Hz at 50 kHz. The decimation factor of the digital filter placed after the SDM in the SD ADC can be controlled so as to reduce the power consumption. Through the use of these techniques in the SD ADC, we can implement reconfigurable sampling rates from 1.5 MS/s to 12.5 MS/s with low power consumption. In order to overcome the limitation of the number of pins for sensor application, a Parallel-to-Serial (P2S) interface is proposed and designed in the receiver. The Low Noise receiver in this paper is implemented in a 0.18 μm CMOS process and the die area is 14.44 mm2. The total power consumption of this chip under a supply voltage of 2.4 V is 46.8 mW. The measured sensitivity and dynamic range are -100 dBV and 100 dB, respectively. The measured SNDR at the output of the SD ADC is 82.02 dB when the input signal frequency and sampling frequency are 7 kHz and 6.25 Msps, respectively.