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High Resolution CMOS Frequency-to-digital Converter for a Fine Dust Sensor using a MEMS Resonator
Hyunwon Moon 대한전자공학회 2022 Journal of semiconductor technology and science Vol.22 No.3
A high resolution, low power CMOS oscillator and frequency-to-digital converter for a fine dust sensor using a MEMS resonator is proposed. The proposed frequency-to-digital converter is realized based on dual-loop hybrid delay-locked loop to distinguish fine frequency variations according to very small fine dust concentrations, and simultaneously applied binary and square search algorithms to obtain accurate digital codes indicating frequency changes. An oscillator and frequency-todigital converter for a fine dust sensor is implemented using the 0.18-μm CMOS process. The core size of the fabricated MEMS oscillator and frequency-to-digital converter is 0.9 mm2 and consumes about 16 mW of power at 1.8 V supply voltage. The proposed frequency-to-digital converter covers the input frequency range of 1.7 GHz to 2.3 GHz with 1 bit resolution of about 3 MHz.
Moon, Hyunwon,Yu, Sunil,Song, Seong-Sik,Nam, Ilku Wiley Subscription Services, Inc., A Wiley Company 2009 MICROWAVE AND OPTICAL TECHNOLOGY LETTERS - Vol.51 No.5
<P>In this article, double-stacked and triple-stacked metal-insulator-metal (MIM) capacitors fabricated in 0.18 μm CMOS process are reported. These provide high-capacitance density of 2 fF/μm<SUP>2</SUP> and 3.2 fF/μm<SUP>2</SUP> and excellent dc and RF characteristics, respectively. The lumped circuit model of the stacked MIM capacitors is presented for high-frequency applications up to 20 GHz. The stacked MIM capacitors offer a reduced chip area for a given capacitance value and are expected to be a viable choice for integration of RF/mixed-mode circuits in a single chip. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 1235–1238, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24305</P>
A Reconfigurable RF-to-DC Converter using an Adaptive Control Loop for a Passive Wake-up Receiver
Hyunwon Moon 대한전자공학회 2021 IEIE Transactions on Smart Processing & Computing Vol.10 No.4
In this paper, a new reconfigurable RF-DC converter structure with an adaptive control loop is proposed for the efficient implementation of passive-type wake-up receivers, which are essential for wireless sensor networks using IoT devices. The proposed reconfigurable RF-to-DC rectifier structure automatically determines the number of rectifier units used for power conversion based on the output DC voltage obtained from the input RF power signal. Thus, high power-conversion efficiency is always maintained regardless of the input RF power level. In addition, a 4-bit switched capacitor bank is used to adjust the impedance matching network required for RF rectifiers. It is automatically configured by the proposed adaptive control loop according to the input RF power. The rectifier was implemented using a 0.25-μm CMOS process. The DC output voltage was obtained with a 100-kΩ load resistor and 915-MHz RF input frequency. When this output voltage is more than 0.5 V, the performance of the converter has a very wide power range of RF input of more than 25 dB (from -22 dBm to 5 dBm). It also has a power conversion efficiency above 30%.
A Low Close-in Phase Noise 2.4 GHz RF Hybrid Oscillator using a Frequency Multiplier
Hyunwon Moon(문현원) 한국산업정보학회 2015 한국산업정보학회논문지 Vol.20 No.1
This paper proposes a 2.4 GHz RF oscillator with a very low close-in phase noise performance. This is composed of a low frequency crystal oscillator and three frequency multipliers such as two doubler (X2) and one tripler (X3). The proposed oscillator is implemented as a hybrid type circuit design using a discrete silicon bipolar transistor. The measurement results of the proposed oscillator structure show -115 dBc/Hz close-in phase noise at 10 kHz offset frequency, while only dissipating 5 mW from a 1-V supply. Its close-in phase noise level is very close to that of a low frequency crystal oscillator with little degradation of noise performance. The proposed structure which is consisted of a low frequency crystal oscillator and a frequency multiplier provides new method to implement a low power low close-in phase noise RF local oscillator.
하이사이드와 로우사이드 LO 신호를 동시에 적용하는 새로운 이미지 제거 수신기 구조
문현원(Hyunwon Moon),류정탁(Jeong-Tak Ryu) 한국산업정보학회 2013 한국산업정보학회논문지 Vol.18 No.2
본 논문에서 높은 주파수 LO 신호와 낮은 주파수 LO신호를 동시에 사용하는 새로운 구조의 이미지 제거 수신기 구조를 제안하였다. 제안된 구조는 기존의 하나의 LO 신호를 사용하는 경우보다 저 잡음 지수 성능과 높은 선형성 특성을 갖는다. 또한 제안된 수신기는 기존의 Weaver 이미지 제거 수신기 구조 보다 같은 이득 error와 위상 error가 존재할 때도 6dB 이상의 높은 이미지 제거 특성을 보인다. 제안된 수신기 구조의 특성을 증명하기 위하여 이득 및 위상 error가 존재할 때의 이미지 제거 특성 공식을 유도하였다. 그리고 이 공식의 유용성을 시스템 시뮬레이션을 통하여 증명하였다. 따라서 높은 이미지 제거 특성 때문에 제안된 새로운 수신기 구조가 이미지 제거 수신기로써 널리 사용이 가능할 것으로 기대한다. In this paper, we propose a new image rejection receiver architecture using simultaneously the high-side and low-side injected LO signals. The proposed architecture has a lower noise figure (NF) performance and a higher linearity characteristic than the previous receiver architecture using a single LO signal. Also, the proposed receiver shows a higher IRR performance about 6dB than that of the previous Weaver image rejection architecture even though the same gain and phase errors between I-path and Q-path exist. To verify these characteristics, we derive an IRR formular of the proposed architecture as a function of mismatch parameters. And we demonstrate its formular"s usefulness through the system simulation. Therefore, the proposed architecture will be widely used to implement the image rejection receiver due to its higher IRR performance.
자동 변환 임피던스 매칭 네트워크를 갖는 CMOS FM 수신기 프론트엔드 구현
김연보(Yeon-Bo Kim),문현원(Hyunwon Moon) 한국산업정보학회 2014 한국산업정보학회논문지 Vol.19 No.4
본 논문에서 2개의 다른 특성을 갖는 FM 안테나들을 사용할 수 있도록 자동 변환매칭 네트워크를 갖는 CMOS FM 수신기 프론트엔드 구조를 제안하였고 이를 65nm CMOS 공정을 이용하여 설계하였다. 제안된 FM 수신기는 높은 주파수 선택 특성을 갖는 임베디드 안테나를 사용 시 FM 전체 주파수 밴드에서 일정한 수신감도를 유지하기 위해서 저 잡음 증폭기의 입력 매칭 회로의 공진 주파수를 채널 주파수에 따라 가변이 가능하도록 구현하였다. 구현된 FM 프론트엔드의 시뮬레이션 결과는 약 38dB 전압이득, 2.5dB 이하의 잡음 지수 특성, -15.5dBm의 IIP3 선형성 특성을 보이고 1.8V 전원에 3.5mA 전류를 소모한다. In this paper, we propose a CMOS FM RX front-end structure with an automatic tunable input matching network and implement it using a 65nm CMOS technology. The proposed FM RX front-end is designed to change the resonance frequency of the input matching network at the low noise amplifier (LNA) according to the channel frequency selected by a phase-locked loop (PLL) for maintaining almost constant sensitivity level when an embedded antenna type with high frequency selectivity characteristic is used for FM receiver. The simulation results of implemented FM front-end show about 38dB of voltage gain, below 2.5dB of noise figure, and -15.5dBm of input referred intercept point (IIP3) respectively, while drawing only 3.5mA from 1.8V supply voltage including an LO buffer.
자동변환 LC 캘리브레이터를 이용한 SAW 필터없는 GPS RX 프론트앤드 구현
김연보(Yeon-Bo Kim),문현원(Hyunwon Moon) 한국산업정보학회 2016 한국산업정보학회논문지 Vol.21 No.1
본 논문에서 PVT 변환에 상관없이 거의 일정한 주파수 특성을 갖는 LC 수동 필터를 구현하기 위해 자동 변환 LC 캘리브레이터를 제안하다. 이를 이용하여 SAW 필터 없는 GPS 수신기 프론트엔드를 65㎚ CMOS 공정을 이용하여 구현하였다. 또한 자동 변환 LC 캘리브레이터에 필요한 신호를 제공하기 위한 새로운 이중 모드 저 잡음 증폭기의 구조를 제안하였다. 구현된 GPS 수신기 프론트엔드의 특성은 약 42.5 ㏈ 전압 이득, 1.35㏈ 이하의 잡음 지수, 가장 최악 조건의 1710 ㎒ 블로커 신호에서 –24 ㏈m의 블로커 입력 P1㏈ 특성을 보이며 이 때 1.2 V 전원에 7 ㎃ 전류를 소모한다. In this paper, new auto㎃tic LC calibrator is proposed for realizing a passive LC filter with almost constant frequency characteristic regardless of the PVT variations. The SAW-less GPS RX front-end is implemented using a 65㎚ CMOS process using the proposed LC calibrator. Also, new dual-mode low noise amplifier (LNA) structure is proposed to generate the RF signal required for the LC calibrator. The characteristics of the implemented GPS RX front-end show the voltage gain of about 42.5 ㏈, noise figure of below 1.35 ㏈, the blocker input P1㏈ of –24 ㏈m in case of the worst blocker signal at 1710 ㎒ frequency, while it consumes 7 ㎃ current at 1.2 V power supply voltage.
A Low Noise and Low Power RF Front-End for 5.8-㎓ DSRC Receiver in 0.13 ㎛ CMOS
Jaeyi Choi,Shin-Hyouk Seo,Hyunwon Moon,Ilku Nam 대한전자공학회 2011 Journal of semiconductor technology and science Vol.11 No.1
A low noise and low power RF front-end for 5.8 ㎓ DSRC (Dedicated Short Range Communication) receiver is presented. The RF front-end is composed of a single-to-differential two-stage LNA and a Gilbert down-conversion mixer. In order to remove an external balun and 5.8 ㎓ LC load tuning circuit, a single-to-differential LNA with capacitive cross coupled pair is proposed. The RF front-end is fabricated in a 0.13 ㎛ CMOS process and draws 7.3 ㎃ from a 1.2 V supply voltage. It shows a voltage gain of 40 ㏈ and a noise figure (NF) lower than 4.5 dB over the entire DSRC band.