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김을년,장준태 대한조선학회 2017 大韓造船學會 論文集 Vol.54 No.6
The purpose of this paper is to verify the structural integrity of a region with numerous penetration-holes in offshore structures such as semi-submersible rig and FPSO. In order to effectively check the yielding and buckling strength of plate members with penetration-holes, a screening analysis program was developed with the FE analysis tool to generate fine meshed model using the theoretical and analysis methods. When a hole is appeared in the plate structure members, the flow of stress is altered such that concentrations of stress form near the hole. Stress concentrations are of concern during both preliminary and detail design and need to be addressed from the perspectives of strength. To configure the geometrical shape, very fine meshed FE analysis is needed as the most accurate method. However, this method is practically impossible to apply for the strength verifications for all perforated plates. In this paper, screening analysis method was introduced to reduce analysis tasks prior to detailed FE analysis. This method is applied to not only the peak stress calculation combined stress concentration factor with nominal stress but also nominal equivalent stress calculation considering cutout effects. The areas investigated by very fine meshed analysis were to be chosen through screening analysis without any reinforcements for penetration-holes. If screening analysis results did not satisfy the acceptance criteria, direct FE analysis method as the 2nd step approach were applied with one of the coarse meshed model considering hole or with the very fine meshed model considering the hole shape and size. In order to effectively perform the local fine meshed analysis, automatic model generating program was developed based on the MSC/PATRAN which is pre-post FE analysis program. Buckling strength was also evaluated by Common Structure Rule (CSR) adopted by IACS as the stress obtained from very fine meshed FE analysis. Due to development of the screening analysis program and automatic FE modeling program, it was able to reduce the design periods and structural analysis costs.
강하라,장준태,Jonghwa Kim,최성진,김동명,김대환 대한전자공학회 2015 Journal of semiconductor technology and science Vol.15 No.5
Positive bias stress-induced instability in amorphous indium-gallium-zinc-oxide (a-IGZO) bottom-gate thin-film transistors (TFTs) was investigated under high VGS/low VDS and low VGS/high VDS stress conditions through incorporating a forward/reverse VGS sweep and a low/high VDS readout conditions. Our results showed that the electron trapping into the gate insulator dominantly occurs when high VGS/low VDS stress is applied. On the other hand, when low VGS/high VDS stress is applied, it was found that holes are uniformly trapped into the etch stopper and electrons are locally trapped into the gate insulator simultaneously. During a recovery after the high VGS/low VDS stress, the trapped electrons were detrapped from the gate insulator. In the case of recovery after the low VGS/high VDS stress, it was observed that the electrons in the gate insulator diffuse to a direction toward the source electrode and the holes were detrapped to out of the etch stopper. Also, we found that the potential profile in the a- IGZO bottom-gate TFT becomes complicatedly modulated during the positive VGS/VDS stress and the recovery causing various threshold voltages and subthreshold swings under various read-out conditions, and this modulation needs to be fully considered in the design of oxide TFT-based active matrix organic light emitting diode display backplane.
해양구조물 설계코드에 기반한 좌굴강도 평가 시스템 개발
김을년,장준태,정장현 대한조선학회 2011 대한조선학회 학술대회자료집 Vol.2011 No.6
FPSO is widely used to develop deep sea oil fields and HHI has constructed nine FPSOs. During these constructions, relevant structural design criteria such as yielding, buckling, fatigue, collision and impact strength were applied to verify structural safety. To apply the buckling strength evaluation for structures, the critical buckling stresses and applied stresses of relevant panels should be calculated. The plate and stiffened panels are to be idealized, which are needed much time and efforts by designers. Therefore, program development is necessary in order to evaluate the buckling strength conveniently and accurately. In this study, the buckling strength assessment system by using offshore code, DNV-RPC201 was developed under MSC/PATRAN, pre-post program of finite element method. Graphic user interface program is written in MSC/PATRAN PCL functions. Source program to evaluate the buckling strength is developed in FORTRAN programming languages
A 0.89 μVrms Noise 93 dB High Dynamic Range Low Power 16 Channels Closed-Loop Neural Recording Chip
조재욱,김장환,장준태,김홍균,김철 한국과학기술원 반도체설계교육센터 2023 IDEC Journal of Integrated Circuits and Systems Vol.9 No.2
The closed-loop neural stimulation system's biggest concern is an artifact with more than tens of mV occurs due to stimulation. Previous studies have digitized the input signals through the analog-to-digital converter (ADC) after using amplifiers to measure tens of μV neural signals. Since the amplifier reduces the input range, the amplifier's output is saturated when a large stimulation artifact appears. This chip design uses the 2nd-order continuous delta-sigma modulator (DSM) to measure signals without saturation even if stimulation artifacts are entered with the neural signal. Overall, circuit structures were designed with a focus on stable operation even if a sudden large signal came in. Also, it can quickly track the sudden change of signals by adding an auto-ranging algorithm. We present 16 channel neural recording chip with a 65-nm CMOS process and the entire chip area is 1 mm2 with 49μW power consumption. Input-referred integrated noise from dc to 500 Hz was 0.89 μVrms, and more than 93 dB input dynamic range were guaranteed.
a-IGZO TFT의 다양한 PBS 조건에 따른 신뢰성 분석
강하라(Hara Kang),장준태(Jun Tae Jang),최성진(Sung-Jin Choi),김동명(Dong Myong Kim),김대환(Dae Hwan Kim) 대한전자공학회 2015 대한전자공학회 학술대회 Vol.2015 No.6
Positive bias stress-induced instability in amorphous indium-gallium-zinc-oxide thin-film transistors were investigated under the condition of VGS/VDS=30V/10V and VGS/VDS=10V/30V stress through incorporating forward/reverse read-out conditions. Through the investigation, we were able to find out that the uniform electron trapping is the dominant mechanism when the VGS/VDS=30V/10V stress is applied. On the other hand, different local VT near the drain and source is caused due to the local electron trapping in the drain and by the local hole trapping near the source when the VGS/VDS=10V/30V stress is applied.