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공간다중화 MIMO 시스템을 위한 MML-DFE기법의 FPGA 구현
임태호,이규인,박창환,정기철,유성욱,김재권,조용수,Im, Tae-Ho,Lee, Kyu-In,Park, Chang-Hwan,Jeong, Ki-Cheol,Yu, Sung-Wook,Kim, Jae-Kwon,Cho, Yong-Soo 한국통신학회 2006 韓國通信學會論文誌 Vol.31 No.11A
ML-DFE(Maximum Likelihood-Decision Feedback Equalization) 기법은 V-BLAST와 같은 공간다중화 MIMO시스템에서 ML 기법의 구현 복잡도를 줄이기 위한 준 최적 신호검출기법으로 불 수 있다. ML-DFE 기법은 ML 기법과 DFE 기법을 결합하여 오차전파를 줄이면서 rich scattering 환경에서 높은 다이버시티 이득을 얻을 수 있다. 본 논문에서는 ML-DFE 기법과 동일한 성능을 보이면서 연산복잡도를 줄일 수 있는 MML-DFE(Modified Maximum Likelihood - Decision Feedback Equalization) 기법을 제안한다. 또한 FPGA 구현을 통하여 제안된 MML-DFE 기법이 기존 ML-DFE 기법에 비하여 구현복잡도를 크게 감소시키면서 동일한 성능을 유지함을 확인한다. The ML-DFE(Maximum Likelihood-Decision Feedback Equalization) can be viewed as either a suboptimal signal detection method for reducing hardware complexity of ML or an enhanced detection method for reducing the effect of error propagation of SIC(Successive Interference Cancellation) in spatially multiplexed MIMO systems such as V-BLAST. The ML-DFE can achieve a higher diversity in rich scattering environments as well as reducing the error propagation effect by combing ML decoding with the DFE. In this paper, an MML-DFE(Modified Maximum Likelihood-Decision Feedback Equalization) is proposed to reduce the hardware complexity of the ML-DFE, without compromising performance. It is shown by FPGA implementation that the proposed MML-DFE can achieve the same performance as the ML-DFE with significantly reduced hardware complexity.
An Efficient Soft-Output MIMO Detection Method Based on a Multiple-Channel-Ordering Technique
임태호,박인수,유현종,유성욱,조용수 한국전자통신연구원 2011 ETRI Journal Vol.33 No.5
In this paper, we propose an efficient soft-output signal detection method for spatially multiplexed multiple-input multiple-output (MIMO) systems. The proposed method is based on the ordered successive interference cancellation (OSIC) algorithm, but it significantly improves the performance of the original OSIC algorithm by solving the error propagation problem. The proposed method combines this enhanced OSIC algorithm with a multiple-channel-ordering technique in a very efficient way. As a result, the log likelihood ratio values can be computed by using a very small set of candidate symbol vectors. The proposed method has been synthesized with a 0.13-μm CMOS technology for a 4x4 16-QAM MIMO system. The simulation and implementation results show that the proposed detector provides a very good solution in terms of performance and hardware complexity.