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나노 부유 게이트 메모리 소자 응용을 위한 실리콘 나노-바늘 구조에 관한 연구
정성욱,유진수,김영국,김경해,이준신,Jung, Sung-Wook,Yoo, Jin-Su,Kim, Young-Kuk,Kim, Kyung-Hae,Yi, Jun-Sin 한국전기전자재료학회 2005 전기전자재료학회논문지 Vol.18 No.12
In this work, nano-needle structures ate formed to solve problem, related to low density of quantum dots for nano floating gate memory. Such structures ate fabricated and electrical properties' of MIS devices fabricated on the nano-structures are studied. Nano floating gate memory based on quantum dot technologies Is a promising candidate for future non-volatile memory devices. Nano-structure is fabricated by reactive ion etching using $SF_6$ and $O_2$ gases in parallel RF plasma reactor. Surface morphology was investigated after etching using scanning electron microscopy Uniform and packed deep nano-needle structure is established under optimized condition. Photoluminescence and capacitance-voltage characteristics were measured in $Al/SiO_2/Si$ with nano-needle structure of silicon. we have demonstrated that the nano-needle structure can be applicable to non-volatile memory device with increased charge storage capacity over planar structures.
습식텍스쳐를 이용한 삼결정 실리콘 광학적.전기적 특성 연구
한규민(Han, Kyu-Min),유진수(Yoo, Jin-Su),유권종(Yoo, Kwon-Jong),이희덕(Lee, Hi-Deok),최성진(Choi, Sung-Jin),권준영(Kwon, Jun-Young),김기호(Kim, Ki-Ho),이준신(Yi, Jun-Sin) 한국신재생에너지학회 2009 한국신재생에너지학회 학술대회논문집 Vol.2009 No.06
Two different wet etching solutions, NaOH 40% and Acid, were used for etching in tri-crystalline Silicon(Tri-Si) solar cell fabrication. The wafers etched in NaOH40% solution showed higher reflectance compared to the wafers etched in Acid solution after SiN_x deposition. In light current-voltage results, the cells etched in Acid solution exhibited higher short circuit current and open circuit voltage than those of the cells etched in NaOH 40% solution. We have obtained 16.70% conversion efficiency in large area(156cm²) Tri-Si solar cells etched in Acid solution.
김도영,김상수,박용관,이준신 成均館大學校 科學技術硏究所 1997 論文集 Vol.48 No.1
본 연구는 최근의 지상전력 응용을 위한 Metal/a-Si:H(n-i-p)/poly-Si(n-p)/Metal 구조를 가지는 적층형 태양전지를 연구하였다. 이 전지는 두 층의 동종접합이 적층된 전지구조로 구성되었다. 상부는 1.8eV의 큰 에너지 밴드갭을 가지는 n-i-p형 a-Si:H와 하부전지는 1.1eV의 작은 에너지 밴드갭의 다결정 규소 전지의 n-p형 접합이다. 태양전지의 효율 영향요소를 PC-1D 태양전지 모의실험을 통해 조사한후 실제 소자 제작에 적용하였다. 주요 연구 분야는 3가지로 구분되며 첫째는 p-n접합 다결정 규소의 하부 전지, 둘째는 p-i-n접합 수소화 비정질 상부규소, 세 번째로 적층형 전지의 계면층에 대한 영향이다. 하부전지의 효율은 900℃의 전열처리, 표면처리, 0.43㎛의 에미터 두께, 상부 Yb 금속, 7% 정도의 태양전지 그리드 면적으로 향상되었다. 최적화된 전지 공정으로부터 약 16%의 변환효율을 달성하였다. 상부전지는 이온에 의한 박막의 손상이 없고 우수한 p/i-a-Si:H 계면층을 가지는 광-CVD 시스템을 사용하여 성장하였다. 적층형 계면효과는 세가지의 화학적인 표면처리, 열산화에 의한 표면처리, 그리고 Yb 금속의 상태등의 경우를 연구하였다. 열산화막에 의해 표면처리된 전지는 높은 광전류의 생성과 향상된 분광반응도를 보이고 있다. We investigated multi-stacked solar cells with a structure of metal/a-Si:H(n-i-p)/ poly-Si(n-p)/metal for the terrestrial applications. This cell consists of two component cells: a top n-i-p junction a-Si:H cell with wide-bandgap 1.8eV and a bottom n-p junction poly-Si cell with narrow-bandgap 1.1eV. The efficiency influencing factors of the solar cell were investigated in terms of simulations and experiments. Three main topics of the investigated study were the bottom cell with n-p junction poly-Si, the top a-Si:H cell with n-i-p junction, and the interface layer effects of multi-stacked cell. The efficiency of bottom cell was improved with a pretreatment temperature of 900℃, surface polishing, emitter thickness of 0.43μm, top Yb metal, and grid finger shading of 7% coverage. The process optimized cell showed a conversion efficiency about 16%. Top cell was grown by using a photo-C JD system which gave an ion damage free and good p/i-a-Si:H layer interface. The multi-stacked interface effect was examined with three different surface states; a chemical passivation, thermal oxide passivation, and Yb metal. The oxide passivated cell exhibited the higher photocurrent generation and better spectral response.
김상수,임동건,이준신,심경석,김홍우,이만근 성균관대학교 1997 학술회의지원논문목록집 Vol.1997 No.-
We investigated grain boundary effect for terrestrial applications of solar cells with low cost, large area, and high efficiency. Grain boundaries are known as potential barriers and recombination centers for the photo generated charge carriers, which make it difficult to achieve a high efficiency cell. To reduce these effects of grain boundarues, we investigated various influencing factors such as thermal treatments various grid patterns selective wet etchings for grain boundarues, buried contact metallizations along grain boundaries, and use of metallic thin films. From the various grid patterns we learned that the series resistance of solar cell reduced open circuit voltage and consequently decreased the cell efficiency. This paper describes the effect of various grid patterns and the employment of metallic thin films for a top electrode.