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- 저자 : 이은철(Eunchoul Lee) (검색결과 3 건)
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최신 SoC 설계를 위한 배치계획에서 사용 가능한 고속배치 알고리즘
이은철(Eunchoul Lee),오성환(Sung-Hwan Oh),김교선(Kyosun Kim) 대한전자공학회 2006 대한전자공학회 학술대회 Vol.2006 No.11
A floorplanner which provides satisfactory speed and suitable results for the modern VLSI design will enable us to optimize the design in an early stage of the complicated and long design flow with little effort. To improve design process and time-to-market of the large-scale and high-complexity System on Chips, we need a fast floorplanner. In this paper, we propose a constructive placement algorithm for large-scale SoC f1oorplan. Towards validating the proposed algorithm, we implemented it on the OpenAccess database. The experimental results of industrial strength examples show the low time complexity which is almost the same as that of the random placement, and the high quality of results which is comparable with the iterative improvement methods.
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Quantum-dot Cellular Automata 회로로부터 디지털 논리 추출
오연보(Younbo Oh),이은철(Eunchoul Lee),김교선(Kyosun Kim) 대한전기학회 2006 대한전기학회 학술대회 논문집 Vol.2006 No.10
Quantum-dot Cellular Automata (QCA) is one of the most promising next generation nano-electronic devices which will inherit the throne of CMOS which is the domineering implementation technology of large scale low power digital systems. In late 1990s, the basic operations of the QCA cell were already demonstrated on a hardware implementation. Also, design tools and simulators were developed. Nevertheless, its design technology is not quite ready for ultra large scale designs. This paper proposes a new approach which enables the QCA designs to inherit the verification methodologies and tools of CMOS designs, as well. First, a set of disciplinary rules strictly restrict the cell arrangement not to deviate from the predefined structures but to guarantee the deterministic digital behaviors. After the gate and interconnect structures of the QCA design are identified, the signal integrity requirements including the input path balancing of majority gales, and the prevention of the noise amplification are checked. And then the digital logic is extracted and stored in the OpenAccess common engineering database which provides a connection to a large pool of CMOS design verification tools. Towards validating the proposed approach, we designed a 2-bit QCA adder. The digital logic is extracted. translated into the Veri log net list. and then simulated using a commercial software.
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오연보(Younbo Oh),이은철(Eunchoul Lee),김교선(Kyosun Kim) 대한전자공학회 2006 대한전자공학회 학술대회 Vol.2006 No.11
Although the functionality of basic gates and interconnect structures of Quantum-dot Cellular Automata (QCA) has been demonstrated on a physical implementation, and the design entry tools and simulators for it have developed, its design technology is not quite ready for ultra large scale designs which have been implemented by the CMOS technology. This paper proposes a new approach which enables the QCA designs to inherit the verification methodologies and tools of CMOS designs, as well. First, a set of disciplinary rules strictly restrict the cell arrangement not to deviate from the predefined structures but to guarantee the deterministic digital behaviors. After the gate and interconnect structures of the QCA design 라e identified, the signal integrity requirements including the input path balancing of majority gates, and the prevention of the noise amplification are checked And then the digital logic is extracted and stored in the OpenAccess common engineering database which provides a connection to a large pool of CMOS design verification tools. Towards validating the proposed approach, we designed a bit slice of an QCA ALU. The digital logic is extracted, translated into the Verilog net list, and then simulated using a commercial software.
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