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Microcontroller based Chaotic Lorenz System for Secure Communication Applications
차민드르 자야위크르마,송한정,Jayawickrama, Chamindra,Song, Hanjung The Korea Institute of Information and Commucation 2018 한국정보통신학회논문지 Vol.22 No.12
본 논문에서는 암호통신 응용을 위한 로렌츠 카오스 회로를 구현한다. 이산형 카오스 로렌츠 시스템을 구현하기 위하여, PIC18F 계열의 마이크로 콘트롤러가 사용되었으며, 제안하는 카오스 회로는, 연산증폭기 기반 아날로그 회로와는 다르게, 8 비트PIC 마이크로 콘트롤러 칩과 3개 R-2R 타입의 디지털-아날로그 변환기로 이루어진다. 마이크로 컨트롤러 포트 B, C 및 D에서 시간 파형 X, Y 및 Z가 출력되도록 하였다. 모의실험을 위하여 MATLAB 및 PROTEUS 소프트웨어 플랫폼이 사용되었다. 제안하는 회로에 대하여, MATLAB 및 프로테우스 프로그램에 의한 모의실험을 통하여 시간파형, 주파수 특성, 2차원 위상특성 해석을 실시하였다. 최종적으로, 카오스 시간파형, 2차원(2D) 어트랙터 가 얻어졌고, 카오스 신호에 기반한 아날로그 신호의 암호통신 검증을 실험을 통하여 확인 하였다. This paper presents a implementation of a chaotic Lorenz system for data secure communication applications. Here we have used PIC18F family-based microcontroller to generate the chaotic signal, and simulated waveform patterns confirm that the chaotic behavior of the microcontroller based discrete time chaotic Lorenz system. There are three R-2R ladder type A/D converters have been implemented for conversion of direct microcontroller digital output into analog waveform, utilizing this specific microcontroller relevant to this experiment work, microcontroller ports B, C and D have been utilized for its time waveform outputs X, Y and Z respectively. XC8 compiler used for the compilation of the program. MATLAB and PROTEUS software platforms are used for simulation. Finally, chaotic time wave forms, 2D chaotic attractors were obtained and secure communication analog waveforms were also verified by experimental measurement.
고밀도 평판형 유도결합 BCl<sub>3</sub>/SF<sub>6</sub> 플라즈마를 이용한 GaAs/AlGaAs와 InGaP 반도체의 선택적 식각에 관한 연구
유승열,류현우,임완태,이제원,조관식,전민현,송한정,이봉주,고종수,고정상,Yoo Seungryul,Ryu Hyunwoo,Lim Wantae,Lee Jewon,Cho Guan Sik,Jeon Minhyon,Song Hanjung,Lee BongJu,Ko Jong Soo,Go Jeung Sang,Pearton S. J. 한국재료학회 2005 한국재료학회지 Vol.15 No.3
We investigated selective dry etching of GaAs over AlGaAs and InGaP in high density planar inductively coupled $BCl_3/SF_6$ plasmas. The process parameters were ICP source power (0-500 W), RE chuck power (0-30W) and gas composition $(60-100\%\;BCl_3\;in\;BCl_3/SF_6)$. The process results were characterized in terms of etch rate, selectivities of GaAs over AlGaAs and InGaP, surface morphology, surface roughness and residues after etching. $BCl_3/SF_6$ selective etching of GaAs showed quite good results in this study. Selectivities of GaAs $(GaAs:AlGaAs\~36:1,\;GaAs:InGaP\~45:1)$ were superior at $18BCl_3/2SF_6$, 20 W RF chuck power, 300 W ICP source power and 7.5 mTorr. Addition of $(5-15\%)SF_6\;to\;BCl_3$ produced relatively high selectivities of GaAs over AlGaAs and InGaP during etching due to decrease of etch rates of AlGaAs and InGaP (boiling points of etch products: $AlF_3\~1300^{\circ}C,\;InF_3>1200^{\circ}C$ at atmosphere) at the condition. SEM and AFM data showed slightly sloped sidewall and somewhat rough surface$(RMS\~9nm)$. XPS study on the surface of processed GaAs proved a very clean surface after dry etching. It shows that planar inductively coupled $BCl_3/SF_6$ plasmas could be a good candidate for selective dry etching of GaAs over AlGaAs and InGaP.
김남태(Namtae Kim),이승환(Seunghwan Lee),송한정(Hanjung Song),이응선(Eungsun Lee),유승교(Seoungkyo Yoo) 대한전기학회 2010 정보 및 제어 심포지엄 논문집 Vol.2010 No.10
Detector design is presented for the measurement of liquid conductivity. which can be applied to the air monitoring in a fabrication process of semiconductor chips and the level detection of water contamination. A conductivity detector is designed so that it can apply an AC reference signal to a conductance test cell and synchronously detect an output signal from the cell by a lock-in amplifier. A lowpass filter after the amplifier extracts a DC component of an amplifier output proportional to the liquid conductivity in the cell. Measured results of an experimental detector are in close agreement with the predicted results. Its linearity is shown to approach to that of a commercially available conductivity detector.
알라딘,차민드라,지성현,응우웬 반하,권유진,송한정,Al-Shidaifat, Ala'aDdin,Jayawickrama, Chamindra,Ji, Sunghyun,Nguyen, Van Ha,Kwon, Yoo-Jin,Song, Hanjung Korea Electric Power Corporation 2016 KEPCO Journal on electric power and energy Vol.2 No.4
In this paper, the chaos-based secure scheme for power line communication is proposed for the first time. A digitalized chaotic generator based Lorenz system is utilized for generating nonlinear dynamic chaotic signal for masking the information signal instead of reported analog chaotic generators. A simple method of encryption and decryption is also given. In order to confirm the feasibility of the proposed scheme, the system is simulated using a simplified encryption/decryption method in Proteus. The gained results from simulation demonstrated that by using the chaos-based security method, the data can be encrypted and easily transmitted through the power line network efficiently.
휴대용 멀티기기를 위한 PFM방식의 승압형 DC-DC 변환기
김지만(Jiman Kim),박용수(Yongsu Park),송한정(Hanjung Song) 大韓電子工學會 2010 電子工學會論文誌 IE (Industry electronics) Vol.47 No.3
본 논문은 휴대용 배터리 구동시스템을 위한 다양한 출력전압(5-7V,100㎃)을 가지는 CMOS DC-DC 변환기를 제안한다. 제안하는 DC-DC 변환기는 Pulse-Frequency Modulation (PFM) 방식을 사용하였고, 기준전압회로, 피드백 저항, 컨트롤러, 내부 파형발생기를 사용하였다. 2개의 외부 수동 소자들 (L,C)을 가진 집적화된 DC-DC 변환기는 0.5㎛ 2-poly 4-metal CMOS 공정에서 설계 되었고 PDA, 휴대폰, 노트북 등에 적용 가능하다. In this paper, we describe a CMOS DC-DC converter with a variable output voltage(5-7V @100㎃) for a portable battery-operated system applications. The proposed DC-DC converter is used along with a Pulse-Frequency Modulation (PFM) method and consists of reference circuit, a feedback resistor, a controller, and an internal oscillator. The integrated DC-DC converter with two external passive components(L,C) has been designed and fabricated on a 0.5㎛ 2-poly 3-metal CMOS process and could be applied to the Personal Digital Assistants(PDA), cellular Phone, Laptop Computer, etc.