Performance and Variation-Immunity Benefits of Segmented-Channel MOSFETs (SegFETs) Using HfO2 or SiO2 Trench Isolation

남효현,박슬기,신창환 대한전자공학회 2014 Journal of semiconductor technology and science Vol.14 No.4

Segmented-channel MOSFETs (SegFETs) can achieve both good performance and variation robustness through the use of HfO2 (a high-k material) to create the shallow trench isolation (STI) region and the very shallow trench isolation (VSTI) region in them. SegFETs with both an HTI region and a VSTI region (i.e., the STI region is filled with HfO2, and the VSTI region is filled with SiO2) can meet the device specifications for high-performance (HP) applications, whereas SegFETs with both an STI region and a VHTI region (i.e., the VSTI region is filled with HfO2, and the STI region is filled with SiO2) are best suited to low-standby power applications. AC analysis shows that the total capacitance of the gate (Cgg) is strongly affected by the materials in the STI and VSTI regions because of the fringing electric-field effect. This implies that the highest Cgg value can be obtained in an HTI/VHTI SegFET. Lastly, the three-dimensional TCAD simulation results with three different random variation sources [e.g., line-edge roughness (LER), random dopant fluctuation (RDF), and work-function variation (WFV)] show that there is no significant dependence on the materials used in the STI or VSTI regions, because of the predominance of the WFV.

Symmetric tunnel field-effect transistor (S-TFET)

남효현,조민희,신창환 한국물리학회 2015 Current Applied Physics Vol.15 No.2

A novel heterojunction symmetric tunnel field-effect transistor (S-TFET) has been proposed and investigated, for the first time, in order to address the inborn technical challenges of the conventional p-i-n TFET (i.e., asymmetric TFET). With a band-to-band tunneling process between the germanium source/ drain region and the silicon channel region, the theoretical limit of the subthreshold slope (SS) can be overcome (i.e., SS ~ 45 mV/decade). The bidirectional current flow in the S-TFET is implemented with a pn- p structure. And better performance in the S-TFET is achieved with a thin silicon-pad layer below the source/drain regions. The effects of source/drain/channel doping concentration and thickness on the performance of the device are investigated in order to create an S-TFET design guideline. In the future, the S-TFET will be one of the promising device structures for ultra-low-power applications, especially in integrated circuits that operate with a half-volt power supply voltage.

1-13GHz Wideband LNA utilizing a Transformer as a Compact Inter-stage Network in 65nm CMOS

남효현,박정동 한국과학기술원 반도체설계교육센터 2017 IDEC Journal of Integrated Circuits and Systems Vol.3 No.2

A low power wide-band low noise amplifier (LNA) is presented in 65 nm CMOS. A compact inter-stage network utilizing one transformer and a resistor is proposed to obtain ultra-wide bandwidth. The designed LNA achieves 1 - 13 GHz bandwidth with > 10 dB of power gain. The simulated noise figure ranges from 9.6 to 10.5 dB over 1-13 GHz with power consumption of 11mW at 1.2 V of power supply.

4 채널 36 Gb/s 27-1 초고속 의사 이진수열 (PRBS) 발생기의 집적화 설계

남효현,박준식,송규하,박정동 대한전자공학회 2018 전자공학회논문지 Vol.55 No.1

In this paper, a 36 Gb/s 27-1 Pseudo-Random Bit Sequence (PRBS) generator is implemented using a 0.13 μm SiGe process. In order to achieve four different 36 Gb/s PRBS patterns from the half-rate PRBS architecture, the output of the 6th latch in the interleaved linear feedback shift register (LFSR) is connected to the input of one XOR, and 0th, 2nd, 3rd, or 5th output of the FF in the LFSR is used to the input of the other XOR. We also implemented a 4×1 clock distribution circuit using three size-reduced Wilkinson power dividers with lumped-elements having the size of 380×380 μm2 to apply clock signals to the same magnitude and phase to four independent PRBS generators. Also, a trigger circuit was designed to verify the normal operation of the PRBS generator. The power consumption per the implemented PRBS generator is 282.5 mW from the 1.2V 및 2.5V power supply voltages, and the size of the individual PRBS generator is 0.5×0.23mm2. 본 논문에서는 36 Gb/s급 27-1 Pseudo-Random Bit Sequence (PRBS) 신호발생기를 0.13μm SiGe 공정을 이용하여 구현하였다. 4 개의 서로 다른 36 Gb/s PRBS 패턴을 half-rate PRBS 구조에서 구현하기 위해 interleaved Linear Feedback Shit Register (LFSR)을 사용하여 6번째 latch의 출력은 항상 XOR의 입력단에 연결 하고 LFSR에서 0,2,3,5 번째 FF의 출력을 XOR의 다른 입력으로 사용하였다. 또한 4개의 독립적인 PRBS 신호발생기에 동일한 크기 및 위상을 가지는 4×1 clock 신호를 인가하기 위하여 Lumped-element를 사용하여 380×380 μm2 크기로 소형화된 3개의 Wilkinson 전력분배기를 이용하여 구현 하였다. 또한 PRBS 신호발생기의 정상동작을 검증하기 위해 trigger회로가 설계되었다. 구현된 PRBS 신호발생기당 전력소모는 1.2V 및 2.5V 전원전압으로부터 282.5 mW이고, 구현된 개별 PRBS 신호 발생기의 크기는 0.5×0.23 mm2이다.

Analysis of Random Variations and Variation-Robust Advanced Device Structures

남효현,이교섭,이현재,박인준,신창환 대한전자공학회 2014 Journal of semiconductor technology and science Vol.14 No.1

In the past few decades, CMOS logic technologies and devices have been successfully developed with the steady miniaturization of the feature size. At the sub-30-nm CMOS technology nodes, one of the main hurdles for continuously and successfully scaling down CMOS devices is the parametric failure caused by random variations such as line edge roughness (LER), random dopant fluctuation (RDF), and work-function variation (WFV). The characteristics of each random variation source and its effect on advanced device structures such as multigate and ultra-thin-body devices (vs. conventional planar bulk MOSFET) are discussed in detail. Further, suggested are suppression methods for the LER-, RDF-, and WFV-induced threshold voltage (VTH) variations in advanced CMOS logic technologies including the double-patterning and double-etching (2P2E) technique and in advanced device structures including the fully depleted silicon-on-insulator (FD-SOI) MOSFET and FinFET/tri-gate MOSFET at the sub-30-nm nodes. The segmented-channel MOSFET (SegFET) and junctionless transistor (JLT) that can suppress the random variations and the SegFET-/JLT-based static random access memory (SRAM) cell that enhance the read and write margins at a time, though generally with a trade-off between the read and the write margins, are introduced.

압축 센싱 수신기용 광대역 전단부 집적화 설계

남효현(Hyohyun Nam),박준식(Junsik Park),송규하(Kyu-Ha Song),박정동(Jung-Dong Park) 대한전자공학회 2018 전자공학회논문지 Vol.55 No.4

본 논문은 압축센싱을 위한 광대역 수신기를 0.13μm SiGe 프로세스를 사용하여 집적화 구현한 것이다. 제안 된 수신기는 광대역 능동 발룬으로 구성된 2-18 GHz 대역 구동 증폭기, 이중 평형 수동 믹서, 그리고 출력 구동 버퍼를 포함하는 700 MHz 4 단 가변 이득 증폭기 (VGA)로 구성된다. 광대역 버퍼는 -10dB 미만의 반사 손실로 20GHz 이상의 대역폭을 달성하기 위해 RF 입력단에서 의사 전송선로를 이용하였다. IF VGA는 15.49 dB에서 34.74 dB의 가변 이득을 조정할 수 있다. 구현 된 수신기는 통합된 64 비트 SPI 스캔 체인 회로에 의해 제어된다. 서브-나이퀴스트 샘플링 기능은 LO 신호용 외부 PRBS 생성기를 통해 검증되었다. 제작된 수신기의 크기는 0.5 × 0.77㎟이고, 2.5V 전원에서 약 27mA의 DC 전류를 소비한다. In this paper, an integrated broadband receiver capable of the compressed sensing is implemented using 0.13μm SiGe process. The proposed receiver consists of a 2-18 GHz driving amplifier configured as the broadband active balun, a double-balanced passive mixer, and a 700-MHz four stage variable gain amplifier (VGA) including an output driving buffer. The broadband buffer utilizes the pseudo transmission-line at the RF input to achieve the more than 20 GHz of the bandwidth with the return loss less than -10 dB. The IF VGA is capable of varying the gain from 15.5 dB to 34.7 dB. The implemented receiver is controlled by an integrated 64-bit SPI scan-chain block. The sub-Nyquist sampling operation has been verified with an external PRBS generator as the LO signal. The receiver chip size is 0.5 × 0.77㎟, and consumes around 27 mA of DC current under 2.5V supply voltage.

65nm CMOS공정을 이용한 FMCW 레이더 및 라디오미터 일체형 센서용 광대역 IF 가변 이득 증폭기

남효현(Hyohyun Nam),김형규(Hyeong-Kyu Kim),김당오(Dang-Oh Kim),류현준(Hyun-Jun Ryu),김주혜(Ju-Hye Kim),박정동(Jung-Dong Park) 대한전자공학회 2018 전자공학회논문지 Vol.55 No.10

본 논문은 FMCW (Frequency-modulated continuous-wave) 레이더 및 레디오미터 센서가 결합된 수신 전단부용 IF 증폭기로 이용할 수 있는 광대역 가변 이득 증폭기 (VGA)를 65nm CMOS 공정을 이용하여 구현한 내용을 다룬다. 구현된 광대역 IF 가변 이득 증폭기는 통합된 64 비트 SPI scan-chain에 의해 제어된다. 구현된 가변 증폭기의 측정된 최대이득은 31.4dB, 가변이득범위는 4.5 dB ~ 31.4 dB, 3-dB 대역폭은 약 2 GHz 이고, 입력단 1dB 이득 압축점 (P1dB)은 -38.81 dBm이다. 본 가변 증폭기는 1.2 V의 전원에서 14.1 mA의 전류를 소모한다. 또한, 가변 이득 증폭기를 구성하는 가변이득단 및 컨트롤 회로, DC 오프셋제거기 및 공통되먹임(CMFB)회로, 출력 버퍼 등, 핵심블록이 차지하고 있는 칩면적은 410 μm × 336 μm이다. In this paper, we present a variable gain amplifier (VGA) that can be used as an IF amplifier block for a combined frequency-modulated continuous-wave (FMCW) radar and radiometer sensor in 65nm CMOS technology. The implemented wideband IF VGA is controlled by an integrated 64-bit SPI scan chain. The fabricated VGA shows the maximum gain of 31.4 dB, the variable gain range of 4.5 dB to 31.4 dB, the 3-dB bandwidth of 2 GHz and the input 1dB gain compression point (P1dB) of -38.81 dBm. The chip consumes 14.1 mA of current at 1.2 V and the chip area occupied by the variable gain stage and its control circuit, DC offset canceller and common-mode feedback (CMFB) circuit, and the output buffer is 410 μm × 336 μm.

비대칭 이득증폭 단위셀을 이용한 2-13 GHz 양방향 증폭기

뉴엔반비엣(Van-Viet Nguyen),남효현(Hyohyun Nam),이복형(Bok-Hyung Lee),이문교(Muk-Kyo Lee),최선열(Sun-Youl Choi),송정문(Jeong-Moon Song),박정동(Jung-Dong Park) 대한전자공학회 2018 전자공학회논문지 Vol.55 No.12

본 논문에서는 이득증폭 비대칭 셀 구조가 결합된 양방향 증폭기 (BDGA) 를 제안한다. 기존의 분산 증폭기 (DA) 설계는 덧셈 이득 메커니즘으로 인한 이득 제한을 보여 주지만, 제안된 구조는 2 개의 BDGA 캐스케이드로 인한 곱셈 이득 메카니즘으로부터 향상된 이득을 얻는다. 또한 BDGA의 출력 전력과 증폭기 이득을 동시에 개선하기 위해서 공통 소스 (CS) 와 캐스코드 (Cascode)가 병렬로 구성되도록 단위 이득 셀을 비대칭으로 구현하였다. 제안된 회로 구조는 표준 0.18 μm CMOS로 제작되었는데, 측정 결과 10.3 dB의 전력 이득을 가지며, 3-dB 대역폭은 2 - 13GHz 범위를 커버한다. 측정된 출력 P1dB는 10GHz에서 8.6 dBm이며, 포화 출력전력은 12.2 dBm이다. 구현된 광대역 양방향 증폭기는 1.8 V 전원전압에서 55 mA의 전류를 소비하며 2.2 × 1.3mm²의 칩 면적을 차지한다. In this paper, we present a bidirectional distributed gain amplifier (BDGA) with asymmetric cell combined with a cascade gain boosting structure. While a conventional distributed amplifier (DA) design shows the gain limitation due to the additive gain mechanism, the proposed structure benefits significantly from multiplicative gain mechanism owing to the cascade of two BDGAs. Moreover, the unit gain cells are intentionally designed to be asymmetrical by combining the common source (CS) and the cascode configuration to improve output power and the gain of the BDGA. The proposed architecture is fabricated in a standard 0.18 μm CMOS. The measurement results exhibit the gain of 8.6 dB, and the 3-dB bandwidth covers the 2 - 13 GHz range. The measured output P1dB is 10.3 dBm along with 12.2 dBm of the saturated output power at 10 GHz. The circuit draws a current of 55 mA from a 1.8 V supply and occupies 2.2 × 0.92 mm² of chip area.

A Wideband Bi-Directional Gain Amplifier with Asymmetric Cell using Cascade Gain Boosting in 65nm CMOS Process

Van Viet Nguyen,남효현,박정동 한국과학기술원 반도체설계교육센터 2019 IDEC Journal of Integrated Circuits and Systems Vol.5 No.2

A bidirectional distributed gain amplifier (BDGA) with asymmetric cell combined with a cascade gain boosting structure is presented in this paper. Conventional DA designs generally have the gain limitation because of the additive gain mechanism, whereas the proposed structure can benefit significantly from the multiplicative gain mechanism due to the cascade of two BDGAs. Moreover, the unit gain cells are intentionally designed to be asymmetrical with the common source (CS) configuration at output stages to improve the output power of the circuit. The proposed circuit architecture is fabricated in a standard 65 nm CMOS. The measurement results show the gain of 10.5 dB, and the 3-dB bandwidth from 5.8 - 17.6 GHz. The measured output P1dB is 6.8 dBm along with 9.3 dBm of the saturated output power at 10 GHz. The circuit draws a current of 75 mA from a 1.2 V supply and occupies 1.1 x 0.6 mm2 of chip area.