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CORDIC을 이용한 디지탈 Quadrature 복조기의 VLSI 구현
남승현,성원용 한국통신학회 1998 韓國通信學會論文誌 Vol.23 No.7
디지탈 quadrature 복조기는 디지탈 통신 시스템에서 변조된 신호의 정확한 위상 복조를 위해 꼭 필요하다. 기존의 방법들은 주로 DDFS(Direct Digital Frequency Synthsizer)를 이용하여 캐리어를 발생시킨 후에 승산기를 이용하여 복조를 수행하였다. 그리고, DDFS에는 주로 ROM(Read Only Memory)을 사용하였는데, 높은 속도와 정확도를 요구하는 경우 ROM의 속도와 크기가 제한이 될 수있다. 이러한 점을 극복하기 위하여 CORDIC(COordinate Rotation Digital Computer) 알고리듬을 사용하여 주파수 합성은 물론 캐리어 복조까지 수행하는 방식을 제안하였다. 최적의 하드웨어 구현을 위해 제한된 단어길이에 의한 영향을 분석하였으며, 하드웨어 비용면에서 ROM을 사용하는 방법과 비교한 결과 약 1/3 정도로 면적이 줄었다. 제안된 구조를 이요한 전주문형 VLSI 구현 결과를 보인다. Digital quadrature demodulator is needed for the coherent demodulation in the digital communication systems such as Binary Phase-Shift-Keying, Quadrature Phase-Shift-Keying, and Quadrature Anmplitude Modulation. Conventaionally, the DDFS (Direct Digital Frequency Synthsizer) is used for generating the carrier signal and seperate multi-pliers are used for mixing. And the DDFS is implemented using the ROM (Read Only Memory), which can be a bottle-neck neck when the fast-speed and small-area implementation is required. A new architecture is developed, which employs the circular rotation mode of the CORDIC algorithm for signal mixing as well as carrier generation. To optimize the hardware design parameters, the finiteword-length effects of the proposed implementation arachitecture are analyzed in comparison with a conventional ROM-based architecture. The hardware costs are also estimated, which showed that the proposed architecture occupies only a third of the area of the conventional ROM-based architecture for the same performance. A full-custom VLSI is developed using the proposed architecture.
남승현,성원용 한국통신학회 1998 韓國通信學會論文誌 Vol.23 No.9
The wordlength optimization for the analog-to-digital converter in DS-CDMA receivers is very important for the efficient implementation of front-end digital demodulator blocks. Wideband CDMA systems reqire a very fast acquisition time, thus they prefer the matched filter base dreceiver architecture.However, the matched filter should san very long chips, and as a results, requires a large number of gates and a high-power consumption. In this paper, the quantization effects on the acquisition performance of the matched filter is analyzed stochastically. The quantization is modeled as a series of saturation and digitization procedures, because the distortion due to the saturation is signal dependent and causes very different effects when compared with that of the, random, digitization noise. Numerical results are obtained to show the optimum saturaton limit of the quantizer for a given wordlength. This analysis can give a guide to low-cost and low-powr digital implementations and assurance of the system performance without intensive simulations.