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Timing Analysis Techniques Review for sub-30 ㎚ Circuit Designs
Juho Kim,Sangwoo Han,Roy Jewell 대한전자공학회 2010 Journal of semiconductor technology and science Vol.10 No.4
With scaled technology, timing analysis of circuits becomes more and more difficult. In this paper, we review recently developed circuit simulation techniques created to deal with the cost issues of transistor-level simulations. Various techniques for fast SPICE simulations and Monte Carlo simulations are introduced. Moreover, process and aging variation issues are mentioned, along with promising methodologies.
Timing Analysis Techniques Review for sub-30 nm Circuit Designs
김주호,Sangwoo Han,Roy Jewell 대한전자공학회 2010 Journal of semiconductor technology and science Vol.10 No.4
With scaled technology, timing analysis of circuits becomes more and more difficult. In this paper, we review recently developed circuit simulation techniques created to deal with the cost issues of transistor-level simulations. Various techniques for fast SPICE simulations and Monte Carlo simulations are introduced. Moreover, process and aging variation issues are mentioned, along with promising methodologies.
Timing Analysis Techniques Review for sub-30 nm Circuit Designs
Kim, Ju-Ho,Han, Sang-Woo,Jewell, Roy The Institute of Electronics and Information Engin 2010 Journal of semiconductor technology and science Vol.10 No.4
With scaled technology, timing analysis of circuits becomes more and more difficult. In this paper, we review recently developed circuit simulation techniques created to deal with the cost issues of transistor-level simulations. Various techniques for fast SPICE simulations and Monte Carlo simulations are introduced. Moreover, process and aging variation issues are mentioned, along with promising methodologies.