http://chineseinput.net/에서 pinyin(병음)방식으로 중국어를 변환할 수 있습니다.
변환된 중국어를 복사하여 사용하시면 됩니다.
趙鍾顯,趙榮一 수원대학교 1994 基礎科學論文集 Vol.3 No.-
Superscalar processors which fetch, decode and execute multiple instructions in every machine cycle, can improve performance of processor according to the number of instructions excuted in parallel. They must support restarting and recovering mechanism to handle precise interrupt and mispredicted branch, and support register renaming and forwarding logic to resolve data dependencies. The most important thing in superscalar processor is interrupt handling mechanism. There are many mechanisms to handle interrupts. The organization and performance of processors are largely influenced by methods to handle the interrupt. This paper discusses several organizations of superscalar processors with priority given to methods a hardware scheme to reduce the hardware complexity of mechanism to handle the interrupt.