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김희규 ( Hee Kyoo Kim ),하승인 ( Seung In Ha ),김유리 ( Yu Ri Kim ),박찬복 ( Chan Bog Park ),옥철호 ( Chul Ho Oak ),장태원 ( Tae Won Jang ),정만홍 ( Maan Hong Jung ),오경승 ( Kyung Seung Oh ),천봉권 ( Bong Kwon Chun ),이민기 ( Min 대한결핵 및 호흡기학회 2004 Tuberculosis and Respiratory Diseases Vol.56 No.5
수율 최적화를 통한 GaAs MMIC 주파수 혼합기 설계
오세홍,양승인 崇實大學校 生産技術硏究所 1995 論文集 Vol.25 No.1
We designed a mixer for PCS receiver in MMIC which promises small chip size by high integration and low cost. Because the mixer was designed by cascoding two single gate MESFETs, we could not only obtain reasonable LO/RF isolation, but also need only a drain - gate bias. The mixer circuit was implemented including transmission lines connecting between components and bonding wire interfacing between the mixer circuit and the chip outside circuit. The circuit design and layout were cone by using HP-EEsof Libra, Academy and Simulatable Artwork Library developed in M/W lab., Soong Sil Univ. Yield analysis was implemented with ±5% parameter variations because MESFET and passive device, which were provided in ETRI Foundry, have some fabrication tolerance. As the results, we obtained initially 77% yield and the Sensitivity Histograms show high sensitivity of yield according to the parameter variations. So, we did the yield optimization, As a result the yield was raised by 13% and the sensitivity becomes dulled. At the final circuit, when the current dissipation is 7mA with 3V drain bias and LO power is 0dBm, the following performances were obtained ; conversion gain > 3.5dB, LO/RF isolation > 16dB, LO/IF isolation > 18dB, 1dB gain compression point = -5.5 dBm(input), third order intercept point = 8.8 dBm(output). The layout chip size becomes 1.5㎜ × 1.5㎜. The mixer would be useful for PCS receiver thanks to its small chip size and low current dissipation.