Automated synthesis of multiple analog circuits using evolutionary computation for redundancy-based fault-tolerance

Kim, Kyung-Joong,Cho, Sung-Bae Elsevier 2012 Applied soft computing Vol.12 No.4

<P><B>Graphical abstract</B></P><P><ce:figure id='fig0085'></ce:figure></P><P><B>Highlights</B></P><P>► We have proposed an ensemble of evolved circuits with a weighted summing circuit. ► The ensemble performed well when removing components. ► The ensemble also performed quite well when there is no component failure.</P> <P><B>Abstract</B></P><P>Analog circuits are one of the most important parts of modern electronic systems and the failure of electronic hardware presents a critical threat to the completion of modern aircraft, spacecraft, and robot missions. Compared to digital circuits, designing fault-tolerant analog circuits is a difficult and knowledge-intensive task. A simple but powerful method for robustness is a redundancy approach to use multiple circuits instead of single one. For example, if component failures occur, other redundant components can replace the functions of broken parts and the system can still work. However, there are several research issues to make the redundant system automatically. In this paper, we used evolutionary computation to generate multiple analog circuits automatically and then we combined the solutions to generate robust outputs. Evolutionary computation is a natural way to produce multiple redundant solutions because it is a population-based search. Experimental results on the evolution of the low-pass, high-pass and band-stop filters show that the combination of multiple evolved analog circuits produces results that are more robust than those of the best single circuit.</P>

디스플레이 IC 내장형 Dual-Port 1T-SRAM를 위한 간단한 시프트 로직 회로를 이용한 데이터라인 리던던시 회로

권오삼,민경식,Kwon, O-Sam,Min, Kyeong-Sik 한국전기전자학회 2007 전기전자학회논문지 Vol.11 No.4

본 논문에서는 Dual-Port 구조를 사용하는 Display IC용 내장형 1T-SRAM에 적합한 간단하고 효과적인 새로운 데이터라인 리던던시 회로(dataline redundancy circuit)를 제안하고 이를 0.18-um CMOS 1T-SRAM 공정을 이용하여 $320{\times}120{\times}18$-Bit Dual-port 1T-SRAM로 구현하여 검증하였다. 한 개의 인버터와 한 개의 낸드 게이트로 이루어진 시프트 로직 회로(shift logic circuit)를 이용해서 기존의 데이터라인 리던던시 회로 보다는 훨씬 간단하게 컨트롤 로직을 구현함으로써 한 개의 비트라인 페어(bit line pair)의 피치(pitch) 내에서 필요한 컨트롤 로직을 모두 구현할 수 있었다. 또한 시프트 로직 회로를 개선해서 worst case에서의 delay를 12.3ns에서 5.9ns로 52% 감소시켜서 워드라인 셋업 후에서 센스앰프 셋업까지의 시간 동안에 데이터라인 스위칭 작업을 완료할 수 있게 하여서 데이터라인 리던던시 회로의 타이밍 오버헤드(timing overhead)를 row cycle 시간에 의해 감추어지게 할 수 있었다. 본 논문에서 제시된 데이터라인 리던던시 회로의 면적 오버헤드(area overhead)는 약 7.6%로 예측된다. In this paper, a simple but effective Dataline Redundancy Circuit (DRC) is proposed for a dual-port 1T-SRAM embedded in Display ICs. The DRC designed in the dual-port $320{\times}120{\times}18$-bit 1T-SRAM is verified in a 0.18-um CMOS 1T-SRAM process. In the DRC, because its control logic circuit can be implemented by a simple Shift Logic Circuit (SLC) with only an inverter and a NAND that is much simpler than the conventional, it can be placed in a pitch as narrow as a bit line pair. Moreover, an improved version of the SLC is also proposed to reduce its worst-case delay from 12.3ns to 5.9ns by 52%. By doing so, the timing overhead of the DRC can be hidden under the row cycle time because switching of the datalines can be done between the times of the word line setup and the sense amplifier setup. The area overhead of the DRC is estimated about 7.6% in this paper.

고속 통신용 CMOS 4.5 Gb/s 인터페이스 회로 구현

김태상(Kim, Tae-Sang),김정범(Kim, Jeong-Beom) 한국전기전자학회 2006 전기전자학회논문지 Vol.10 No.2

본 논문에서는 고속 통신용 인터페이스 회로를 RMVL(redundant multi-valued logic)을 이용하여 CMOS 회로로 설계하였다 설계한 1:4 디멀티플렉서 (demuitiplexer, serial-parallel convertor)는 직렬 데이터를 병렬 redundant 다치 데이터로 변환하는 부호화 회로와 redundant 다치 데이터를 병렬 이진 데이터로 변환하는 복호화 회로로 구성된다. 이 회로는 0.35um 표준 CMOS 공정을 이용하여 구현하였으며, 기존의 이진 논리회로보다 고속 동작을 한다. 이 회로는 3.3V의 공급전원에서 4.5Gb/s 이상의 동작속도와 53mW의 전력소모를 가지며, 동작속도는 0.35um 공정이 가지는 최대 주파수에 의해 제한된다. 설계한 회로가 높은 동작 주파수를 가지는 미세공정상에서 사용될 경우 100b/s 이상의 고속 통신용 인터페이스 구현이 가능하다. This paper describes a high speed interface circuit using redundant multi-valued logic for high speed communication ICs. This circuit is composed of encoding circuit that serial binary data are received and converted into parallel redundant multi-valued data, and decoding circuit that converts redundant multi-valued data to parallel binary data. Because of the multi-valued data conversion, this circuit makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, the proposed 1:4 DEMUX (demultiplexer, serial-parallel converter), was designed using a 0.35um standard CMOS technology. Proposed DEMUX is achieved an operating speed of 4.5Gb/s with a supply voltage of 3.3V and with power consumption of 53mW. The operating speed of this circuit is limited by the maximum frequency which the 0.35um process has. Therefore, this circuit is to achieve CMOS communication ICs with an operating speed greater than 10Gb/s in submicron process of high operating frequency.

비동기 이중화 시스템의 센서 SENT protocol 신호 간 단락 고장 검출 알고리즘에 관한 사례 연구

서동균(Dongkyun Seo),황대훈(Daehun Hwang) 한국자동차공학회 2022 한국자동차공학회 부문종합 학술대회 Vol.2022 No.6

In a redundant distributed system due to functional safety, etc., the physical distance between controllers may be very close. If the physical distance is close, there is a high possibility of interference between the controller and the connected sensor signal line. To prevent this, SAE J2716 SENT (Single Edge Nibble Transmission) is used, but when a short circuit occurs between physical lines, there is a case where the failure cannot be detected. In this case, an erroneous signal may be transmitted to the controller and pose a risk to the driver. To solve this problem, this paper describes a case study for detecting a failure when a physical short circuit occurs in each controller sensor signal line for the SENT signal of the sensor used in the asynchronous redundant vehicle distributed system controller.

이중화 구조를 이용한 비동기 디지털 시스템의 방사선 고장 극복

곽성우(Seong Woo Kwak),양정민(Jung-Min Yang) 제어로봇시스템학회 2014 제어·로봇·시스템학회 논문지 Vol.20 No.6

Asynchronous digital circuits working in military and space environments are often subject to the adverse effects of radiation faults. In this paper, we propose a new hardening technique against radiation faults. The considered digital system has the structure of DMR (Double Modular Redundancy), in which two sub-systems conduct the same work simultaneously. Based on the output feedback, the proposed scheme diagnoses occurrences of radiation faults and realizes immediate recovery to the normal behavior by overriding parts of memory bits of the faulty sub-system. As a case study, the proposed control scheme is applied to an asynchronous dual ring counter implemented in VHDL code.

스위칭이 가능한 여유 구조를 가진 비동기 순차 회로의 내고장성 구현

곽성우(Seong Woo Kwak),양정민(Jung-Min Yang) 한국지능시스템학회 2017 한국지능시스템학회논문지 Vol.27 No.4

본 논문에서는 스위칭 여유 구조를 가진 비동기 순차 머신에서 고장 극복을 위한 교정 제어 방법을 제안한다. 하나의 비동기 순차 머신 모듈에서 고장이 발생하면 고장이 없는 다른 여유 모듈로 전환하여 고장을 극복하는 방식이다. 고장이 없는 다른 모듈로 전환하는 과정과 전환된 모듈의 상태를 원래 모듈의 상태와 동일하게 하는 과정은 비동기 교정 제어 기법을 사용하여 실현한다. 또한 고장 극복을 위한 교정 제어기의 존재 조건을 규명하고 상세한 설계 과정을 제시한다. 제안된 제어 기법을 FPGA로 구현한 ROM 인터페이스 회로에 적용하여 그 효용성을 실험적으로 검증한다. In this paper, we propose a corrective controller in order to tolerate transient and permanent faults in asynchronous sequential machines with hardware redundancy and switching capability. If a fault is detected in an active module, it is switched to a redundant module to avoid the fault. The switching and state recovery process is performed asynchronously by a corrective controller. We address the existence condition and detailed design procedures for the proposed corrective controllers that overcome state transition faults. To show its validity and advantage, the proposed contrlloer is applied to a ROM interface circuit implemented on FPGA.

철도차량용 배터리팩의 신뢰성 향상을 위한 배터리셀 구성방안 연구

조인호(In-ho Cho) 한국철도학회 2023 한국철도학회논문집 Vol.26 No.1

EEPROM Emulation기반 차량용 ECU의 기능 안전을 고려한 비 휘발성 메모리 접근 향상 기법

강민희(Minhee Kang),고희권(Heekwon Ko) 한국자동차공학회 2015 한국자동차공학회 부문종합 학술대회 Vol.2015 No.5

A non-volatile memory access for automotive ECUs is used for various purposes including application data, calibration parameters, diagnostic trouble codes, reprogramming or non-volatile memory data access through CAN / XCP protocols. Recently the demands of providing the non-volatile information to the complete system requires the different data processing depending on the data types capable to influence the functional safety concept or the interface types such as read only data, cyclic data or immediate data without decreasing the performance. This paper describes a non-volatile memory access speed improvement scheme to store data while securing and monitoring damaged data using EEPROM Emulation.

순환 중복 검사를 통해 전송 오류를 검출하는차량용 반도체 직렬 인터페이스

최지웅,임형철,양성현,이동현,이명진,이성수 한국전기전자학회 2022 전기전자학회논문지 Vol.26 No.3

This paper proposes a CRC error verification method for SPI and I2C buses of automotive semiconductors. Inautomotive semiconductors, when an error occurs in communication and an incorrect value is transmitted, fatalresults may occur. Unlike LIN communication and CAN communication, in communication such as SPI and I2C,there is no frame for detecting an error, so some definitions of new standards are required. Therefore, in thispaper, the CRC error detection mode is newly defined in the SPI and I2C communication protocols, and theverification is presented by designing it in hardware.