저전력 BLE/ZigBee IoT MCU 용 RF transciever 설계 연구

정지학,김응주 한국지식정보기술학회 2020 한국지식정보기술학회 논문지 Vol.15 No.1

Recently, the demand of BLE/ZigBee IoT MCU is highly increased for low power sensor network realization. In this paper, a low power and low cost BLE/ZigBee RF transceiver is studied with careful review of Bluetooth 5.0 core specification for BLE and IEEE 802.15.4 ZigBee specification. For the receiver side, a low-IF architecture with digital filtering and high ADC dynamic range is used to eliminate the analog filter to achieve both of small size and low power consumption simultaneously. Thanks to the inherent characteristics of a low-IF receiver, the proposed architecture also has the merits of high performance because of no signal loss due to DC offset removal filter and no flicker noise. For the transmitter side, a direct frequency modulation based on two point modulation and gain and phase mismatch calibration is proposed also for low power consumption. Moreover, 5bit binary-weighted inverse class-F power amplifier is proposed because the inverse class-F power amplifier shows greatly improved power efficiency even better than that of the class-F power amplifier. The 5bit binary-weighting is used for maximum transmit output power control as well as transmitter ramping for on-to-off and off-to-on transition. To meet FCC spurious emission regulation, on-chip and off-chip LC filtering and LO duty ratio control to suppress 3rd harmonic and 2nd harmonic, respectively. Finally, this paper presents the power architecture, which can support battery operation and solid power supply operation for best power efficiency and BOM cost optimization.

설계툴을 사용한 저전력 SoC 설계 동향

박남진,주유상,나중찬,Park, Nam Jin,Joo, Yu Sang,Na, Jung-Chan 한국전자통신연구원 2020 전자통신동향분석 Vol.35 No.2

Small portable devices such as mobile phones and laptops currently display a trend of high power consumption owing to their characteristics of high speed and multifunctionality. Low-power SoC design is one of the important factors that must be considered to increase portable time at limited battery capacities. Popular low power SoC design techniques include clock gating, multi-threshold voltage, power gating, and multi-voltage design. With a decreasing semiconductor process technology size, leakage power can surpass dynamic power in total power consumption; therefore, appropriate low-power SoC design techniques must be combined to reduce power consumption to meet the power specifications. This study examines several low-power SoC design trends that reduce semiconductor SoC dynamic and static power using EDA tools. Low-power SoC design technology can be a competitive advantage, especially in the IoT and AI edge environments, where power usage is typically limited.

A Hybrid Self-Powered System Based on Wind Energy Harvesting for Low-Power Sensors on Canyon Bridges

Hao Cao,Xiaoping Wu,Hao Wu,Yajia Pan,Dabing Luo,Ali Azam,Zutao Zhang 한국정밀공학회 2023 International Journal of Precision Engineering and Vol.10 No.1

Canyon cross wind has great potential to be transformed into electricity to power for low-power sensors of the health monitoring devices in bridge field. In this paper, a hybrid wind energy harvesting system (WEHS), integrating piezoelectric and electromagnetic mechanisms, is proposed to supply power for low-power sensors on canyon bridges. Firstly, the S-rotor embedded with a one-way bearing converts wind energy into rotational mechanical energy. Then, the piezoelectric cantilever beam and coils simultaneously convert mechanical energy into electricity under the excitation of the rotational magnet array. For the piezoelectric transducer, the symmetrical poles arrangement of tip magnet reduces the starting wind speed and resistance torque during energy harvesting. In addition, the relationship between different number of excitation magnets and the output of the piezoelectric transducer is explored. Finally, the output electricity is stored in the capacitors to supply power for low power sensors. The experimental results showed that the symmetrical poles arrangement of tip magnet could effectively reduce the starting resistance torque and improve the output power at low wind speeds. Given a wind speed of 6.5 m/s, the maximum output power of the WEHS can reach 19.24 mW with corresponding electrical energy of 75.714 mJ in one sweep period (6 s). The field test results demonstrated that the WEHS could effectively charge for the capacitors and power for a hundred LEDs. Furthermore, the mechanical durability and stability of the WEHS are verified by introducing a self-powered low power sensor system.

사회적 배제와 권력 수준이 많은 노력 제품(vs. 적은 노력 제품)의 선호에 미치는 효과

박세훈,김채영 한국마케팅학회 2020 마케팅연구 Vol.35 No.2

In modern society, social exclusion is a common experience to anyone and power level is formed in any group. This research examines the effects of these factors on the preference for effortful products. First, socially excluded consumers feel uncomfortable tension caused by lack of control, so they try to work hard in their goal pursuit processing, thus restoring their sense of control. On the basis of this mechanism, following hypotheses are proposed. Consumers in the social exclusion(vs. social inclusion) condition will prefer high-effort products(vs. low-effort products)(H1), and this effect will be mediated by the perceived control level(H2). However, consumers in the high-power condition are not affected by the low control level caused by social exclusion because they already have enough sense of control. Therefore, we predict that the social exclusion effect on preference for the high-effort products(vs. low-effort products) will be attenuated by high power(vs. low power) condition(H3). To test our hypotheses, we conducted two experiments. In experiment 1, we used one-factor(social connection) two-level(social inclusion vs. social exclusion) between-subjects design and manipulated effort level by advertising slogan. The results confirmed that socially excluded participants prefer high-effort products(vs. low-effort products) compared with socially included ones, and this effect is mediated by their sense of control. In experiment 2, we used 2(social connection: social inclusion vs. social exclusion) x 2(power level: low power vs. high power) between-subjects design and the results supported our prediction that the social exclusion effect is disappeared in high power condition, while it is maintained in low power condition. Finally, we discuss the theoretical and managerial implications of our findings and provide the limitations and directions for the future research. 사회적 배제는 현대사회에서 누구나 보편적으로 느끼는 감정이며, 권력의 차이는 어느 집단에서나 형성된다. 본 연구에서는 이러한 특성들이 많은 노력(vs. 적은 노력)을 필요로 하는 제품에 대한 선호에 미치는 영향을 조사하 였다. 먼저, 사회적 배제 상태에 있는 소비자들은 낮은 통제감으로 인한 불편함을 경험하고, 이를 해소하기 위해 목표 추구 과정에서 더 큰 노력을 하여서 자신의 통제감을 회복시키고자 한다. 이러한 매커니즘을 기반으로, 다 음과 같은 가설을 설정하였다. 사회적 배제(vs. 사회적 포함) 조건의 소비자들은 목표 달성을 위해 많은 노력 제 품(vs. 적은 노력 제품)을 선호할 것이고(가설1), 이는 지각된 통제감 수준에 의해 매개될 것이다(가설2). 그러 나 높은 권력 상태에 있는 소비자들은 이미 충분한 통제감을 갖고 있기 때문에 사회적 배제로 인한 낮은 통제감 에 영향을 받지 않으리라 예상하였다. 따라서 높은 권력 조건(vs. 낮은 권력 조건)에서는 많은 노력 제품(vs. 적 은 노력 제품)의 선호에 대한 사회적 배제의 효과가 약화 내지는 사라질 것이라는 가설3을 설정하였다. 가설 검증을 위해 두 차례의 실험을 실시했다. 먼저, 실험 1에서는 1요인(사회적 연결) 2수준(사회적 포함 vs. 사회적 배제) 집단 간 요인 설계를 사용했고, 광고문구를 통해 실험 제품의 노력수준을 조작했다. 그 결과, 사회적 배제(vs. 사회적 포함) 조건에서 많은 노력 제품(vs. 적은 노력 제품)에 대한 상대적 선호도가 더 높았 고, 이 효과는 지각된 통제감 수준에 의해 매개되는 것으로 나타났다. 실험 2에서는 2(사회적 연결: 사회적 포함 vs. 사회적 배제) x 2(권력 수준: 낮은 권력 vs. 높은 권력) 집단 간 요인 설계를 활용하여, 많은 노력 제품(vs. 적은 노력 제품)의 선호에 대한 사회적 배제 효과가 낮은 권력 조건에서는 나타나지만 높은 권력 조건에서는 사 라지는 것을 확인하였다. 마지막으로 본 연구를 통해 얻을 수 있는 이론적, 실무적 시사점을 밝히고, 연구가 갖 는 한계점과 미래의 연구 방향을 제시하였다.

배터리와 태스크를 고려한 저전력 알고리듬 연구

윤충모(Choong-Mo Youn),김재진(Jae-Jin Kim) 한국디지털콘텐츠학회 2014 한국디지털콘텐츠학회논문지 Vol.15 No.3

In this paper, we proposed the low power algorithm consider the battery and the task. The proposed algorithm setting the power consumption of unit time consider the capacity of the battery and the target time. Calculate the power consumption of all tasks. Calculate the average power consumption by the task have maximum power consumption and the task have minimum power consumption. Recalculate average power consumption consider the unit time of task. Compare calculated average power consumption and average power consumption of task. Compared results, low power algorithm processing the average power consumption less than or equal calculated power consumption of task. Low-power algorithm is greater than the average power consumption of the task to perform targeted tasks. Low-power processors and the task by dividing the power consumption of the device in large part for the low-power consumption is performed. Experiments [6] were compared with the results of the power consumption. The experimental results [6] is reduced power consumption than the efficiency of the algorithm has been demonstrated.

MSP430 기반 저전력 뇌 신경자극기 S/W 설계 및 구현

홍상표(Sangpyo Hong),권성호(Cheng-Hao Quan),심현민(Hyun-Min Shim),이상민(Sangmin Lee) 대한전자공학회 2016 전자공학회논문지 Vol.53 No.7

인체 삽입형 뇌 신경자극기는 소비전력에 있어서 효율적인 구조로 설계되어야 한다. 이들 자극신호는 파형이 단순하고, MCU(micro controller unit)의 대기시간은 실행시간보다 훨씬 긴 특성을 가짐에도 불구하고, 이러한 특성을 고려한 저전력 설계가 되어 있지 않다. 본 논문에서는 자극신호 특성에 기반하는 저전력 알고리즘을 제안한다. 또한 뇌 신경자극기 S/W, NMS(neuro modulation simulation)의 설계 및 구현 결과도 제시한다. 저전력 알고리즘 구현을 위해, 기존 뇌 신경자극기 프로그램의 함수별 수행(running) 시간을 분석하여, 실행(execution) 시간과 대기(waiting) 시간을 도출하였다. 그리고 AMLPM(active mode-low power mode) 전환시간을 추정하여 저전력 알고리즘 구현에 반영하였다. 본 논문에서 제안하는 저전력 알고리즘은 자극신호의 특성을 이용하여 출력을 다수의 구간으로 분할하고, MCU를 구간별 AM 또는 LPM으로 운용한다. 제안하는 알고리즘의 검증을 위해, 외부 제어프로그램을 개발하여 알고리즘의 동작상태를 확인하였고, 오실로스코프를 이용하여 출력신호의 정확성을 확인하였다. 검증 결과, 제안하는 저전력 알고리즘을 적용할 경우, 기존 뇌 신경자극기 대비 소모전류를 76.31% 감소시킴을 확인 할 수 있었다. A power-efficient neuromodulator is needed for implantable systems. In spite of their stimulation signal’s simplicity of wave shape and waiting time of MCU(micro controller unit) much longer than execution time, there is no consideration for low-power design. In this paper, we propose a novel of low-power algorithm based on the characteristics of stimulation signals. Then, we designed and implement a neuromodulation software that we call NMS(neuro modulation simulation). In order to implement low-power algorithm, first, we analyze running time of every function in existing NMS. Then, we calculate execution time and waiting time for these functions. Subsequently, we estimate the transition time between active mode (AM) and low-power mode (LPM). By using these results, we redesign the architecture of NMS in the proposed low-power algorithm: a stimulation signal divided into a number of segments by using characteristics of the signal from which AM or LPM segments are defined for determining the MCU power reduces to turn off or not. Our experimental results indicate that NMS with low-power algorithm reducing current consumption of MCU by 76.31 percent compared to NMS without low-power algorithm.

Low-Swing 기술을 이용한 저 전력 CVSL 전가산기 설계

강장희,김정범,Kang Jang Hee,Kim Jeong Beom 대한전자공학회 2005 電子工學會論文誌-SD (Semiconductor and devices) Vol.42 No.2

본 논문은 기존의 CVSL 전가산기 회로 내부에 Low-Swing 기술의 특성을 갖도록 NMOS 트랜지스터를 추가하여 감소된 출력전압으로 동작하는 CVSL 전가산기를 제안하였다. 또한 제안한 Low-Swing CVSL 전가산기를 이용하여 $8\times8$ 병렬 곱셈기를 구성한 후 회로의 성능을 평가하였다. 본 논문에서 제안한 Low-Swing CVSL 전가산기 회로는 $13.1\%$의 전력감소와 $14.3\%$의 전력소모와 지연시간의 곱(power-delay-product) 감소가 이루어졌다 Hynix $0.35{\mu}m$ 표준 CMOS 공정을 사용하여 HSPICE로 시뮬레이션하고 그 동작 특성을 검증하였다. In this paper, we propose a new Low-Swing CVSL full adder for low power consumption. An $8\times8$ parallel multiplier is used for the comparison between the proposed Low-Swing CVSL full adder with conventional CVSL full adder. Comparing the previous works, this circuit is reduced the power consumption rate of $13.1\%$ and the power-delay-product of $14.3\%$. The validity and effectiveness of the proposes circuits are verified through the HSPICE under Hynix $0.35{\mu}m$ standard CMOS process.

Effect of Pulp Properties on the Power Consumption in Low Consistency Refining

( Huan Liu ),( Jixian Dong ),( Kai Qi ),( Xiya Guo ),( Ying Yan ),( Lijie Qiao ),( Chuanwu Duan ),( Zhiming Zhao ) 한국목재공학회 2020 목재공학 Vol.48 No.6

The power consumption in the low consistency (LC) refining is an important indicator for the optimal control of the process and it is composed of the net power and the no-load power. The refining efficiency and process characterization of LC refining are directly affected by power consumption. In this paper, the effect of pulp consistency and average fiber length on the power consumption and refining efficiency were studied through the LC refining trials conducted by an experimental disc refiner. It is found that the curve of power-gap clearance can be divided into constant power section, power reduction section, and power increase section. And the no-load power and the adjustable domain of loading applied by the refining plates will increase as the increase of pulp consistency, while the increase of net power is larger than that of no-load power which makes the increasing of refining efficiency. Meanwhile, the adjustable domain of loading applied by the refining plates can be slightly improved by increasing the average fiber length, but its effect on the no-load power in the LC refining process can be neglected. The study of power consumption in LC refining is of positive significance for the proper selection of pulp properties in LC refining, in-depth exploration of refining mechanism, and energy consumption reduction in refining.

필터방식 얼굴검출 하드웨어의 저전력 설계

김윤구(Yoon-Gu Kim),정용진(Yong-Jin Jeong) 대한전자공학회 2008 電子工學會論文誌-SD (Semiconductor and devices) Vol.45 No.6

본 논문에서는 필터방식 얼굴검출 하드웨어를 저전력 설계하고 그에 따른 전력 소모량을 분석하였다. 얼굴검출 하드웨어는 입력되는 영상에서 얼굴의 위치를 검출하며 내부적으로 6개 모듈과 11개의 모듈 간 버퍼가 삽입되어 각 모듈이 순환 연산한다. 따라서 저전력 설계를 위해 SLEEP 모드와 ACTIVE 모드를 적용하였고, 해당 하드웨어에 모듈별 그리고 레지스터별 클럭게이팅(Clock Gating) 기술을 적용하였다. 추가적으로 모듈간 버퍼는 메모리 파티션을 통해 메모리에서 소비하는 전력양을 줄였으며 게이트 레벨에서도 저전력 설계 기술(Gate level power optimization)을 적용하였다. 이는 삼성 0.18um 공정의 STD130 라이브러리를 사용하여 Synopsis(사)의 Power-Compiler를 통해 구현되었으며 동사의 Prime-Power에 의해 소비 전력량을 측정하였다. 그 결과 저전력 설계 기술을 적용하기 전과 비교하여 ACTIVE 모드일 경우 약 68%의 전력 소모를 줄였다. In this paper, we designed a low power face detection hardware and analysed its power consumption. The face detection hardware was fabricated using Samsung 0.18um CMOS technology and it can detect multiple face locations from a 2-D image. The hardware is composed of 6 functional modules and 11 internal memories. We introduced two operating modes(SLEEP and ACTIVE) to save power and a clock gating technique was used at two different levels: modules and registers. In additional, we divided an internal memory into several pieces to reduce the energy consumed when accessing memories, and fully utilized low power design option provided in Synopsis Design Compiler. As a result, we could obtain 68% power reduction in ACTIVE mode compared to the original design in which none of the above low power techniques were used.

Deep Submicron 공정의 멀티미디어 SoC를 위한 저전력 움직임 추정기 아키텍쳐

연규성,전치훈,황태진,이성수,위재경 대한전자공학회 2004 電子工學會論文誌-SD (Semiconductor and devices) Vol.41 No.10

본 논문에서는 0.13㎛ 이하의 deep sub-micron 공정처럼 누설 전류가 심한 공정을 이용하여 멀티미디어 SoC를 설계할 때, 가장 전력 소모가 높은 움직임 추정 기법의 전력 소모를 줄이기 위한 저전력 움직임 추정기의 아키텍쳐를 제안하였다. 제안하는 아키텍쳐는 기존의 동적 전력 소모만을 고려한 구조와는 달리 정적 전력 소모까지 고려하여 누설 전류가 심한 공정에 적합한 구조로, 효율적인 전력 관리가 필수적인 동영상 전화기 등의 각종 휴대용 정보기기 단말기에 적합한 형태이다. 제안하는 아키텍쳐는 하드웨어 구현이 용이한 전역 탐색 기법 (full search)을 기본으로 하며 동적 전력 소모를 줄이기 위하여 조기 은퇴(early break-off) 기법을 도입하였다. 또한 정적 전력 소모를 줄이기 위하여 전원선 잡음을 고려한 메가블록 전원 차단 기법을 사용하였다. 제안된 아키텍쳐를 멀티미디어 SoC에 적용하였을 때의 효용성을 검증하기 위해 시스템 수준의 제어 흐름과 저전력 제어 기법을 개발하였으며, 이를 바탕으로 시스템 수준에서의 소모 전력을 계산하였다. 모의실험 결과 0.13㎛ 공정에서 전력 소모가 50% 정도로 감소함을 확인할 수 있었다. 선폭의 감소와 칩 내부 발열량의 증가로 인한 누설 전류의 증가를 고려할 때, 기존의 동적 전력 소모만을 고려한 구조는 전력 감소 효율이 점점 나빠짐에 반하여 제안하는 움직임 추정기 아키텍쳐는 안정적인 전력 감소 효율을 보여주었다. This paper propose a motion estimator architecture to reduce the power consumption of the most-power-consuming motion estimation method when designing multimedia SoC with deep submicron technologies below 0.13${\mu}{\textrm}{m}$. The proposed architecture considers both dynamic and static power consumption so that it is suitable for large leakage process technologies, while conventional architectures consider only dynamic power consumption. Consequently, it is suitable for mobile information terminals such as mobile videophone where efficient power management is essential. It exploits full search method for simple hardware implementation. It also exploits early break-off method to reduce dynamic power consumption. To reduce static power consumption, megablock shutdown method considering power line noise is also employed. To evaluate the proposed architecture when applied multimedia SoC, system-level control flow and low-power control algorithm are developed and the power consumption was calculated based on thor From the simulation results, power consumption was reduced to about 60%. Considering the line width reduction and increased leakage current due to heat dissipation in chip core, the proposed architecture shows steady power reduction while it goes worse in conventional architectures.