Wafer-Scale Arrays of Nonvolatile Polymer Memories with Microprinted Semiconducting Small Molecule/Polymer Blends

Bae, Insung,Hwang, Sun Kak,Kim, Richard Hahnkee,Kang, Seok Ju,Park, Cheolmin American Chemical Society 2013 ACS APPLIED MATERIALS & INTERFACES Vol.5 No.21

<P>Nonvolatile ferroelectric-gate field-effect transistors (Fe-FETs) memories with solution-processed ferroelectric polymers are of great interest because of their potential for use in low-cost flexible devices. In particular, the development of a process for patterning high-performance semiconducting channel layers with mechanical flexibility is essential not only for proper cell-to-cell isolation but also for arrays of flexible nonvolatile memories. We demonstrate a robust route for printing large-scale micropatterns of solution-processed semiconducting small molecules/insulating polymer blends for high performance arrays of nonvolatile ferroelectric polymer memory. The nonvolatile memory devices are based on top-gate/bottom-contact Fe-FET with ferroelectric polymer insulator and micropatterned semiconducting blend channels. Printed micropatterns of a thin blended semiconducting film were achieved by our selective contact evaporation printing, with which semiconducting small molecules in contact with a micropatterned elastomeric poly(dimethylsiloxane) (PDMS) mold were preferentially evaporated and absorbed into the PDMS mold while insulating polymer remained intact. Well-defined micrometer-scale patterns with various shapes and dimensions were readily developed over a very large area on a 4 in. wafer, allowing for fabrication of large-scale printed arrays of Fe-FETs with highly uniform device performance. We statistically analyzed the memory properties of Fe-FETs, including ON/OFF ratio, operation voltage, retention, and endurance, as a function of the micropattern dimensions of the semiconducting films. Furthermore, roll-up memory arrays were produced by successfully detaching large-area Fe-FETs printed on a flexible substrate with a transient adhesive layer from a hard substrate and subsequently transferring them to a nonplanar surface.</P><P><B>Graphic Abstract</B> <IMG SRC='http://pubs.acs.org/appl/literatum/publisher/achs/journals/content/aamick/2013/aamick.2013.5.issue-21/am402852y/production/images/medium/am-2013-02852y_0006.gif'></P><P><A href='http://pubs.acs.org/doi/suppl/10.1021/am402852y'>ACS Electronic Supporting Info</A></P>

Vertically stacked microscale organic nonvolatile memory devices toward three-dimensional high integration

Yoo, D.,Song, Y.,Jang, J.,Hwang, W.T.,Jung, S.H.,Hong, S.,Lee, J.K.,Lee, T. Elsevier Science 2015 Organic electronics Vol.21 No.-

In this study, vertically stacked microscale organic resistive nonvolatile memory devices are demonstrated. The fabricated devices consisted of vertically stacked two layers of 32x32 crossbar-structured organic memory devices (total of 2048 memory cells) with a memory-cell size of 7x7μm<SUP>2</SUP> on a SiO<SUB>2</SUB> substrate. The microscale organic memory devices were made using an orthogonal photolithography technique with a highly fluorinated photoresist and development solvent. The vertically stacked microscale organic memory devices showed reproducibility with good endurance, and stability and long retention times (over 10<SUP>4</SUP>s) for both layers. The realization of vertical stacking of microscale organic memory devices might enable the production of organic memory devices toward the three-dimensional integration of organic electronic devices.

Solution-processed nonvolatile Hf-doped ZnO thin-film transistor memory with SiO₂ micro- and nanoparticles as a trapping medium

Kumar, Manoj,Jeong, Hakyung,Lee, Dongjin Elsevier 2018 Materials science and engineering B. Advanced Func Vol.236 No.-

<P><B>Abstract</B></P> <P>We report a nonvolatile-memory device based on solution-processed Hf-doped ZnO (ZnO:Hf) thin-film transistors (TFTs) fabricated by inserting SiO<SUB>2</SUB> microparticles (MPs) and nanoparticles (NPs) as a charge trapping medium. The transfer characteristics of ZnO:Hf TFT devices inserted with SiO<SUB>2</SUB> particles showed a large clockwise hysteresis behavior owing to charge carrier trapping capability. Both memory devices exhibited a highly programmable memory window during the program/erase operation, which can be attributed to charge carrier trapping and de-trapping in SiO<SUB>2</SUB> particles. Particularly, the memory device with SiO<SUB>2</SUB> NPs revealed a larger memory window over 25 V than that with MPs. Furthermore, the fabricated memory devices showed remarkably long-term retention characteristics and the ON/OFF current ratio greater than 10<SUP>4</SUP>.</P> <P><B>Highlights</B></P> <P> <UL> <LI> SiO<SUB>2</SUB> MPs and NPs are utilized for the first time for trapping and de-trapping of charge carriers in TFTs-based memory. </LI> <LI> The nonvolatile-memory device exhibited excellent wide programmable windows. </LI> <LI> The memory showed long-term retention characteristics and exhibited an ON/OFF current ratio greater than 10<SUP>4</SUP>. </LI> </UL> </P>

Small Molecular Organic Nonvolatile Memory Cells Fabricated with in Situ O₂ Plasma Oxidation

Sung-Ho Seo,Woo-Sik Nam,Jea-Gun Park 대한전자공학회 2008 Journal of semiconductor technology and science Vol.8 No.1

We developed small molecular organic nonvolatile 4F² memory cells using metal layer evaporation followed by O₂ plasma oxidation. Our memory cells sandwich an upper α-NPD layer, Al nanocrystals surrounded by Al₂O₃, and a bottom α-NPD layer between top and bottom electrodes. Their nonvolatile memory characteristics are excellent: the Vth, Vp (program), Ve (erase), memory margin (Ion/Ioff), data retention time, and erase and program endurance were 2.6V, 5.3V; 8.5V, ?1.5×10², 1×10<SUP>5</SUP>s, and 1×10³ cycles, respectively. They also demonstrated symmetrical current versus voltage characteristics and a reversible erase and program process, indicating potential for terabit-level nonvolatile memory.

Small Molecular Organic Nonvolatile Memory Cells Fabricated with in Situ O₂ Plasma Oxidation

Seo, Sung-Ho,Nam, Woo-Sik,Park, Jea-Gun The Institute of Electronics and Information Engin 2008 Journal of semiconductor technology and science Vol.8 No.1

We developed small molecular organic nonvolatile $4F^2$ memory cells using metal layer evaporation followed by $O_2$ plasma oxidation. Our memory cells sandwich an upper ${\alpha}$-NPD layer, Al nanocrystals surrounded by $Al_2O_3$, and a bottom ${\alpha}$-NPD layer between top and bottom electrodes. Their nonvolatile memory characteristics are excellent: the $V_{th},\;V_p$ (program), $V_e$ (erase), memory margin ($I_{on}/I_{off}$), data retention time, and erase and program endurance were 2.6 V, 5.3 V, 8.5 V, ${\approx}1.5{\times}10^2,\;1{\times}10^5s$, and $1{\times}10^3$ cycles, respectively. They also demonstrated symmetrical current versus voltage characteristics and a reversible erase and program process, indicating potential for terabit-level nonvolatile memory.

Progress of High-k Dielectrics Applicable to SONOS-Type Nonvolatile Semiconductor Memories

Zhenjie Tang,Zhiguo Liu,Xinhua Zhu 한국전기전자재료학회 2010 Transactions on Electrical and Electronic Material Vol.11 No.4

As a promising candidate to replace the conventional floating gate flash memories, polysilicon-oxide-nitride-oxidesilicon (SONOS)-type nonvolatile semiconductor memories have been investigated widely in the past several years. SONOS-type memories have some advantages over the conventional floating gate flash memories, such as lower operating voltage, excellent endurance and compatibility with standard complementary metal-oxide-semiconductor (CMOS) technology. However, their operating speed and date retention characteristics are still the bottlenecks to limit the applications of SONOS-type memories. Recently, various approaches have been used to make a trade-off between the operating speed and the date retention characteristics. Application of high-k dielectrics to SONOS-type memories is a predominant route. This article provides the state-of-the-art research progress of high-k dielectrics applicable to SONOS-type nonvolatile semiconductor memories. It begins with a short description of working mechanism of SONOS-type memories, and then deals with the material ’ requirements of high-k dielectrics used for SONOS-type memories. In the following section, the microstructures of high-k dielectrics used as tunneling layers, charge trapping layers and blocking layers in SONOS-type memories, and their impacts on the memory behaviors are critically reviewed. The improvement of the memory characteristics by using multilayered structures, including multilayered tunneling layer or multilayered charge trapping layer are also discussed. Finally, this review is concluded with our perspectives towards the future researches on the high-k dielectrics applicable to SONOS-type nonvolatile semiconductor memories.

Progress of High-k Dielectrics Applicable to SONOS-Type Nonvolatile Semiconductor Memories

Tang, Zhenjie,Liu, Zhiguo,Zhu, Xinhua The Korean Institute of Electrical and Electronic 2010 Transactions on Electrical and Electronic Material Vol.11 No.4

As a promising candidate to replace the conventional floating gate flash memories, polysilicon-oxide-nitride-oxidesilicon (SONOS)-type nonvolatile semiconductor memories have been investigated widely in the past several years. SONOS-type memories have some advantages over the conventional floating gate flash memories, such as lower operating voltage, excellent endurance and compatibility with standard complementary metal-oxide-semiconductor (CMOS) technology. However, their operating speed and date retention characteristics are still the bottlenecks to limit the applications of SONOS-type memories. Recently, various approaches have been used to make a trade-off between the operating speed and the date retention characteristics. Application of high-k dielectrics to SONOS-type memories is a predominant route. This article provides the state-of-the-art research progress of high-k dielectrics applicable to SONOS-type nonvolatile semiconductor memories. It begins with a short description of working mechanism of SONOS-type memories, and then deals with the materials' requirements of high-k dielectrics used for SONOS-type memories. In the following section, the microstructures of high-k dielectrics used as tunneling layers, charge trapping layers and blocking layers in SONOS-type memories, and their impacts on the memory behaviors are critically reviewed. The improvement of the memory characteristics by using multilayered structures, including multilayered tunneling layer or multilayered charge trapping layer are also discussed. Finally, this review is concluded with our perspectives towards the future researches on the high-k dielectrics applicable to SONOS-type nonvolatile semiconductor memories.

Nonvolatile Memory Characteristics of Double-Stacked Si Nanocluster Floating Gate Transistor

Kim, Eun-Kyeom,Kim, Kyong-Min,Son, Dae-Ho,Kim, Jeong-Ho,Lee, Kyung-Su,Won, Sung-Hwan,Sok, Jung-Hyun,Hong, Wan-Shick,Park, Kyoung-Wan The Institute of Electronics and Information Engin 2008 Journal of semiconductor technology and science Vol.8 No.1

We have studied nonvolatile memory properties of MOSFETs with double-stacked Si nanoclusters in the oxide-gate stacks. We formed Si nanoclusters of a uniform size distribution on a 5 nm-thick tunneling oxide layer, followed by a 10 nm-thick intermediate oxide and a second layer of Si nanoclusters by using LPCVD system. We then investigated the memory characteristics of the MOSFET and observed that the charge retention time of a double-stacked Si nanocluster MOSFET was longer than that of a single-layer device. We also found that the double-stacked Si nanocluster MOSFET is suitable for use as a dual-bit memory.

Four-level Nonvolatile Small-molecule Memory-cell Embedded with Fe Nanocrystals Surrounded with an FeO and Fe2 O3 Tunneling Barrier

Sung-Ho Seo,Woo-Sik Nam,박광희,박재근 한국물리학회 2010 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.57 No.6

We developed a nonvolatile cross-bar 4F2 small molecule (Alq3: aluminum tris (8-hydroxyquinoline)) memory cell embedded with Fe nanocrystals surrounded by an FeO and Fe2 O3 tunneling barrier. The memory cell demonstrates a memory margin (Ion/Ioff ratio) of ∼7.44 × 102 and a retention-time of ∼105 sec for four current levels (I off: 2.73 × 10−8, I int2: 5.87 × 10 −7, Iint1: 3.64 × 10−6, and Ion: 2.03 × 10-5 A), which can probably be extended to ten years. Memory cells of this type follow a current conduction mechanism with space-charge-limited-current and F-N tunneling for nonvolatile memory cell operation.

Nonvolatile Memory Characteristics of Double-Stacked Si Nanocluster Floating Gate Transistor

Eunkyeom Kim,Kyongmin Kim,Daeho Son,Jeongho Kim,Kyungsu Lee,Sunghwan Won,Junghyun Sok,Wan-Shick Hong,Kyoungwan Park 대한전자공학회 2008 Journal of semiconductor technology and science Vol.8 No.1

We have studied nonvolatile memory properties of MOSFETs with double-stacked Si nanoclusters in the oxide-gate stacks. We formed Si nanoclusters of a uniform size distribution on a 5 nm-thick tunneling oxide layer, followed by a 10 nm-thick intermediate oxide and a second layer of Si nanoclusters by using LPCVD system. We then investigated the memory characteristics of the MOSFET and observed that the charge retention time of a double-stacked Si nanocluster MOSFET was longer than that of a single-layer device. We also found that the double-stacked Si nanocluster MOSFET is suitable for use as a dual-bit memory.