Self-assembled wide bandgap nanocoatings enabled outstanding dielectric characteristics in the sandwich-like structure polymer composites

Wang Tian-Yu,Li Xiao-Fen,Liu Shu-Ming,Liu Bai-Xin,Liang Xi-Dong,Li Shunning,Zhang Gui-Xin,Liu Jian-Bo,Dang Zhi-Min 나노기술연구협의회 2022 Nano Convergence Vol.9 No.55

Polymer dielectrics are insulators or energy storage materials widely used in electrical and electronic devices. Polymer dielectrics are needed with outstanding dielectric characteristics than current technologies. In this study, the self-assembly of boron nitride nanosheets (BNNSs) was applied to form an inorganic–organic nanocoating on various common polymer dielectrics. It is inexpensive and easy to fabricate this thin coating on a large scale. The coating has a wide bandgap and thus can significantly improve the breakdown strength of polymer dielectrics. The charge characteristics and trapping parameters of nano-domains on the surfaces of polymer dielectrics were measured, and the coating had shallow trap levels. This facilitated the dissipation of surface charges and thus greatly increased the flashover voltage. The coating also effectively improved the temperature stability and dielectric constant of the polymer dielectric. This nanocoating shows potential as a method to effectively improve the dielectric characteristics of polymer dielectrics and outperform existing composite polymer dielectrics, which are crucial for large-scale applications in energy storage and power and electronic devices.

Surface-Modified High-k Oxide Gate Dielectrics for Low-Voltage High-Performance Pentacene Thin-Film Transistors

Kim, C. S.,Jo, S. J.,Lee, S. W.,Kim, W. J.,Baik, H. K.,Lee, S. J. Wiley - VCH Verlag GmbH & Co. KGaA 2007 Advanced Functional Materials Vol.17 No.6

<P>In this study, pentacene thin-film transistors (TFTs) operating at low voltages with high mobilities and low leakage currents are successfully fabricated by the surface modification of the CeO<SUB>2</SUB>–SiO<SUB>2</SUB> gate dielectrics. The surface of the gate dielectric plays a crucial role in determining the performance and electrical reliability of the pentacene TFTs. Nearly hysteresis-free transistors are obtained by passivating the devices with appropriate polymeric dielectrics. After coating with poly(4-vinylphenol) (PVP), the reduced roughness of the surface induces the formation of uniform and large pentacene grains; moreover, –OH groups on CeO<SUB>2</SUB>–SiO<SUB>2</SUB> are terminated by C<SUB>6</SUB>H<SUB>5</SUB>, resulting in the formation of a more hydrophobic surface. Enhanced pentacene quality and reduced hysteresis is observed in current–voltage (I–V) measurements of the PVP-coated pentacene TFTs. Since grain boundaries and –OH groups are believed to act as electron traps, an OH-free and smooth gate dielectric leads to a low trap density at the interface between the pentacene and the gate dielectric. The realization of electrically stable devices that can be operated at low voltages makes the OTFTs excellent candidates for future flexible displays and electronics applications.</P> <B>Graphic Abstract</B> <P>Enhanced pentacene quality and reduced hysteresis are observed in the current–voltage (I–V) measurements for poly(4-vinylphenol) (PVP)-coated pentacene thin-film transistors (TFTs: see figure). Since grain boundaries and OH groups are believed to trap electrons, an OH-free and smoother gate dielectric is favorable for the formation of the interface between the pentacene and gate dielectric with a low trap density. <img src='wiley_img/1616301X-2007-17-6-ADFM200600747-content.gif' alt='wiley_img/1616301X-2007-17-6-ADFM200600747-content'> </P>

Novel electrodes and gate dielectrics for field-effecttransistors based on two-dimensional materials

송인택 대한화학회 2023 Bulletin of the Korean Chemical Society Vol.44 No.6

Two-dimensional (2D) materials are atomically thin materials that show quan-tum confinement effect. They have been studied as promising materials forfield-effect transistors (FETs). The fabrication of an FET mainly concerns how todeposit metal electrodes and dielectrics onto the 2D material channel. Andconventional fabrication processes are not optimized for novel applications of2D FETs. This review aims to introduce recent studies regarding novel elec-trodes and dielectrics for 2D FETs. The devices made by these approachesshow comparable performance to conventional FETs. And they feature newapplications and easy fabrication. This review covers the topics in two sections:evaporation-free electrodes and nonoxide dielectrics. The former covers elec-trodes prepared without direct deposition of metals using evaporators or sput-ters. The latter encompasses alternatives to oxide dielectrics. These topicswould be beneficial to realize the intrinsic properties of 2D materials and toassist fundamental research with prototyping FETs on a tabletop.

Effect of Polymer Gate Dielectrics on Charge Transport in Carbon Nanotube Network Transistors: Low-<i>k</i> Insulator for Favorable Active Interface

Lee, Seung-Hoon,Xu, Yong,Khim, Dongyoon,Park, Won-Tae,Kim, Dong-Yu,Noh, Yong-Young American Chemical Society 2016 ACS APPLIED MATERIALS & INTERFACES Vol.8 No.47

<P>Charge transport in carbon nanotube network transistors strongly depends on the properties of the gate dielectric that is in direct contact with the semiconducting carbon nanotubes. In this work, we investigate the dielectric effects on charge transport in polymer-sorted semiconducting single-walled carbon nanotube field-effect transistors (s-SWNT-FETs) by using three different polymer insulators: A low-permittivity (epsilon(r)) fluoropolymer (CYTOP, epsilon(r) = 1.8), poly(methyl methacrylate) (PMMA, epsilon(r) = 3.3), and a high-epsilon(r) ferroelectric relaxor [P(VDF-TrFE-CTFE), epsilon(r) = 14.2]. The s-SWNT-FETs with polymer dielectrics show typical ambipolar charge transport with high ON/OFF ratios (up to similar to 10(5)) and mobilities (hole mobility up to 6.77 cm(2) V-1 s(-1) for CYTOP). The s-SWNT-FET with the lowest-k dielectric, CYTOP, exhibits the highest mobility owing to formation of a favorable interface for charge transport, which is confirmed by the lowest activation energies, evaluated by the fluctuation-induced tunneling model (FIT) and the traditional Arrhenius model (E-aFIT = 60.2 meV and E-aArr = 10 meV). The operational stability of the devices showed a good agreement with the activation energies trend (drain current decay similar to 14%, threshold voltage shift similar to 0.26 V in p-type regime of CYTOP devices). The poor performance in high-epsilon(r) devices is accounted for by a large energetic disorder caused by the randomly oriented dipoles in high-k dielectrics. In conclusion, the low-k dielectric forms a favorable interface with s-SWNTs for efficient charge transport in s-SWNT-FETs.</P>

Cyclodextrin-based reactive porogen for nanoporous ultra-low dielectrics

Min, Sung-Kyu,Moon, Bongjin,Kim, Hyunjung,Rhee, Hee-Woo Elsevier 2011 Current Applied Physics Vol.11 No.1

<P><B>Abstract</B></P><P>We prepared ultralow dielectrics with remarkably high mechanical strengths (E ∼ 8.1 GPa and H ∼ 1.2 GPa). The reactivity of porogens was critical to enhanced mechanical properties of ULK. In the case of non-reactive porogens the mechanical properties of nanoporous ultralow dielectrics dramatically decreased with reduction in dielectric constant. However, reactive CD was very effective in the preparation of ULK for the next generation semiconductors.</P> <P><B>Highlights</B></P><P>► We examined the effect of porogen reactivity on the properties of dielectrics. ► Cyclodextrin was functionalized as a reactive porogen with alkoxy silane groups. ► Reactivity of porogens was critical to the enhanced mechanical properties. ► But the reactivity did not affect the dielectrical properties. ► Reactive CD produced the utmost modulus and hardness of nanoporous dielectrics.</P>

Metal Gate and High-k Gate Dielectrics for sub 50 nm High Performance MOSFETs

Hokyung Park,Musarrat Hasan,Minseok Jo,Hyunsang Hwang 대한금속재료학회(구 대한금속학회) 2007 ELECTRONIC MATERIALS LETTERS Vol.3 No.2

Over the past few years, metal gates and high-k gate dielectrics have been intensively developed to implement sub 50nm CMOS technology. Nevertheless, some issues of metal gate and high-k gate dielectric need to be solved. In particular, the high density of traps in dielectric and workfunction modulation with metal gate should be addressed by either understanding the mechanism or developing a new process. In this paper, we propose an analyses method and various processes to understand and solve the problems of metal gate and high-k gate dielectrics. First, to effectively passivate high-k/Si interface traps, post metallization annealing in high pressure hydrogen ambient was investigated. Compared with conventional forming gas annealing, high pressure annealing showed improved device performance owing to the effective passivation of interface traps. Second, the effect of traps in the high-k layer was evaluated by single pulsed I(d)-V(g) measurement and reliability such as bias temperature instability. By using nano-scale analysis, we have confirmed that non-uniform oxygen vacancy causes charge trapping and reliability degradation. Then, the interaction of metal gate and gate dielectric during thermal process was investigated with various metal electrodes and systems. Metal/dielectric interaction was found to be severe in elemental and ternary metal electrodes, while the binary metal electrode showed minimum interaction. To achieve appropriate workfunction with minimal interaction, the bi-layer metal electrode and conducting oxide electrode were developed. Both electrodes showed suitable workfunction which is close to conduction and valance band of silicon with improved thermal stability.

Characteristics of ZnO-based TFT Using La2O3 High-k Dielectrics

문연건,Sih Lee,박종완,김도현,Je-Hun Lee,정창오 한국물리학회 2009 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.55 No.5

In order to reduce the operation voltage of the ZnO-based thin film transistors (ZnO-TFTs), we fabricate devices using amorphous La2O3 high-k dielectrics. ZnO, as a channel layer, and ITO, as source/drain electrodes, are deposited by DC magnetron sputtering, and La2O3 high-k dielectrics are deposited by using electron cyclotron resonance-atomic layer deposition (ECR-ALD). The deposition conditions of the gate insulator were optimized for leakage current, breakdown field, and high device performance. ZnO-TFTs with high-k La2O3 gate insulators exhibited good performance. The average channel mobility, turn-on voltage, ratio of the on current to the off current, and subthreshold swing were 0.77 cm2/Vs, −0.8 V, 105, and 1.2 V/decade, respectively. We compared the characteristics of a device consisting of La2O3 to those of a device consisting of SiO2 to examine their potential for use as high-k dielectrics in future TFT devices. In order to reduce the operation voltage of the ZnO-based thin film transistors (ZnO-TFTs), we fabricate devices using amorphous La2O3 high-k dielectrics. ZnO, as a channel layer, and ITO, as source/drain electrodes, are deposited by DC magnetron sputtering, and La2O3 high-k dielectrics are deposited by using electron cyclotron resonance-atomic layer deposition (ECR-ALD). The deposition conditions of the gate insulator were optimized for leakage current, breakdown field, and high device performance. ZnO-TFTs with high-k La2O3 gate insulators exhibited good performance. The average channel mobility, turn-on voltage, ratio of the on current to the off current, and subthreshold swing were 0.77 cm2/Vs, −0.8 V, 105, and 1.2 V/decade, respectively. We compared the characteristics of a device consisting of La2O3 to those of a device consisting of SiO2 to examine their potential for use as high-k dielectrics in future TFT devices.

Advances in atomic layer deposited high-κ inorganic materials for gate dielectrics engineering of two-dimensional MoS2 field effect transistors

Zhang Ling,Xing Houying,Yang Meiqing,Dong Qizhi,Li Huimin,Liu Song 한국탄소학회 2022 Carbon Letters Vol.32 No.5

Molybdenum disulfide (MoS2) has been one of the most promising members of transition-metal dichalcogenides materials. Attributed to the excellent electrical performance and special physical properties, MoS2 has been broadly applied in semiconductor devices, such as field effect transistors (FETs). At present, the exploration of further improving the performance of MoS2-based FETs (such as increasing the carrier mobility and scaling) has encountered a bottleneck, and the application of high-κ gate dielectrics has become an effective approach to change this situation. Atomic layer deposition (ALD) enables high-quality integration of MoS2 and high-κ gate dielectrics at the atomic level. In this review, we summarize recent advances in the fabrication of two-dimensional MoS2 FETs using ALD high-κ materials as gate dielectrics. We first briefly discuss the research background of MoS2 FETs. Second, we expound the electrical and other essential properties of high-κ gate dielectrics, which are essential to the performance of MoS2 FETs. Finally, we focus on the advances in fabricating MoS2 FETs with ALD high-κ gate dielectrics on MoS2, as well as the optimized ALD processes. In addition, we also look forward to the development prospect of this field.

Hybrid dielectrics composed of Al2O3 and phosphonic acid self-assembled monolayers for performance improvement in low voltage organic field effect transistors

Jang Sukjae,Son Dabin,황선빈,Kang Minji,Lee Seoung-Ki,Jeon Dae-Young,Bae Sukang,Lee Sang Hyun,이동수,Kim Tae-Wook 나노기술연구협의회 2018 Nano Convergence Vol.5 No.20

Low voltage operational organic transistors (< 4 V) based on pentacene were successfully fabricated with hybrid dielectric films composed of aluminum oxide using atomic layer deposition and various phosphonic acid-based self-assembled monolayers as the gate dielectrics. High capacitances up to 279 nF/cm2, low leakage current densities of 10−8 A/cm2 at 6 V, and high breakdown fields up to 7.5 MV/cm were obtained. The transistors with the octadecylphosphonic acid hybrid dielectric exhibited an improved saturation mobility of 0.58 cm2/Vs, a subthreshold slope of 151 mV/decade, a threshold voltage of − 1.84 V and an on–off current ratio of 106. The low surface energies of the self-assembled monolayers having non-polar terminal groups, such as methyl and pentafluorophenoxy, improved the carrier conduction of the transistors due to the pentacene growth with an edge-on orientation for low voltage operation. The pentafluorophenoxy end-group showed an accumulation of holes at the semiconductor-dielectric interface.

Atomic Layer Deposition of Dielectrics on Graphene Using Reversibly Physisorbed Ozone

Jandhyala, Srikar,Mordi, Greg,Lee, Bongki,Lee, Geunsik,Floresca, Carlo,Cha, Pil-Ryung,Ahn, Jinho,Wallace, Robert M.,Chabal, Yves J.,Kim, Moon J.,Colombo, Luigi,Cho, Kyeongjae,Kim, Jiyoung American Chemical Society 2012 ACS NANO Vol.6 No.3

<P>Integration of graphene field-effect transistors (GFETs) requires the ability to grow or deposit high-quality, ultrathin dielectric insulators on graphene to modulate the channel potential. Here, we study a novel and facile approach based on atomic layer deposition through ozone functionalization to deposit high-κ dielectrics (such as Al<SUB>2</SUB>O<SUB>3</SUB>) without breaking vacuum. The underlying mechanisms of functionalization have been studied theoretically using <I>ab initio</I> calculations and experimentally using <I>in situ</I> monitoring of transport properties. It is found that ozone molecules are physisorbed on the surface of graphene, which act as nucleation sites for dielectric deposition. The physisorbed ozone molecules eventually react with the metal precursor, trimethylaluminum to form Al<SUB>2</SUB>O<SUB>3</SUB>. Additionally, we successfully demonstrate the performance of dual-gated GFETs with Al<SUB>2</SUB>O<SUB>3</SUB> of sub-5 nm physical thickness as a gate dielectric. Back-gated GFETs with mobilities of ∼19 000 cm<SUP>2</SUP>/(V·s) are also achieved <I>after</I> Al<SUB>2</SUB>O<SUB>3</SUB> deposition. These results indicate that ozone functionalization is a promising pathway to achieve scaled gate dielectrics on graphene without leaving a residual nucleation layer.</P><P><B>Graphic Abstract</B> <IMG SRC='http://pubs.acs.org/appl/literatum/publisher/achs/journals/content/ancac3/2012/ancac3.2012.6.issue-3/nn300167t/production/images/medium/nn-2012-00167t_0007.gif'></P><P><A href='http://pubs.acs.org/doi/suppl/10.1021/nn300167t'>ACS Electronic Supporting Info</A></P>