http://chineseinput.net/에서 pinyin(병음)방식으로 중국어를 변환할 수 있습니다.
변환된 중국어를 복사하여 사용하시면 됩니다.
- 中文 을 입력하시려면 zhongwen을 입력하시고 space를누르시면됩니다.
- 北京 을 입력하시려면 beijing을 입력하시고 space를 누르시면 됩니다.
RISS 인기검색어
- 검색키워드
- 주제어 : Through glass via (검색결과 14 건)
- 무료
- 기관 내 무료
- 유료
-
Shin, Young-min,Kim, Yong-Kweon,Lee, Seung-Ki,Shin, Hyogeun,Cho, Il-Joo,Park, Jae-Hyoung Elsevier 2019 Sensors and actuators. B, Chemical Vol.290 No.-
<P><B>Abstract</B></P> <P>This paper presents the fabrication and measurements of a vertical out-of-plane microprobe electrode array with individual interconnects through the substrate using a silicon through-glass via (TGV) with transparent properties. The TGV was fabricated using a low-resistance silicon (LRS) via and the glass reflow process. The microprobe structure was formed by multiple deep reactive ion etching and reactive ion etching processes using one-step photolithography and a single etch mask. The height and pitch of the microprobe are designed to be 90 μm and 210 μm, respectively. Cr and Au conductive layers were deposited and patterned on the silicon microprobe structure. A parylene-C thin film was used as an insulating layer and it was etched only at the tip-end through the self-alignment fabrication process using a thick photoresist to expose the conductive part. Each microprobe electrode was independently connected to the backside of the substrate through the silicon TGV. The single via resistance was measured to be 1.26 ± 0.041 Ω. To verify the electrochemical characteristics of the microprobe electrodes with individual interconnects, the steady-state limiting current through the redox reaction was measured by the cyclic voltammetry method for each electrode. The measured steady-state peak current of the microprobe electrode was compared with the theoretical calculation. Further, the electrode impedance was measured and the equivalent circuit analysis was constructed using the Zview impedance modeling software. Experiments were conducted to measure the impedance of 16 microprobe electrodes, and it was confirmed that the impedance did not exceed 1 MΩ at 1 kHz. Then, primary rat cortical neuron cells (DIV 7) were cultured on the fabricated microprobe electrodes and neural spike signals were successfully measured. Also, the light transmittance experiment was conducted to measure the transparency of the TGV structure fabricated through the glass reflow process.</P> <P><B>Highlights</B></P> <P> <UL> <LI> The silicon-based microprobe structure was fabricated through the multiple DRIE and RIE processes with one-step photolithography and single etch mask. </LI> <LI> Each microprobe electrode was independently connected to the backside of the substrate through the silicon through glass via. </LI> <LI> During the glass reflow process, the melted glass is reflowed and filled up entirely between the silicon pillars. Through this glass reflow process, the microprobe electrode has high light transmission properties. </LI> <LI> The fabricated microprobe based electrode array was characterized with the cyclic voltammetry measurements and electrochemical impedance spectroscopy measurement. </LI> <LI> Neural spike signals were measured using the fabricated microprobe electrode. </LI> </UL> </P>
-
Miniaturized and high-performance RF packages with ultra-thin glass substrates
Kim, Min Suk,Pulugurtha, Markondeya Raj,Kim, Youngwoo,Park, Gapyeol,Cho, Kyungjun,Smet, Vanessa,Sundaram, Venky,Kim, Joungho,Tummala, Rao Elsevier 2018 Microelectronics Journal Vol.77 No.-
<P><B>Abstract</B></P> <P>Advanced RF packages are demonstrate with active (low-noise amplifier, RF switch) and passive integration in ultra-thin 3D glass packages with miniaturization and enhanced performance. The novelty of this RF packages is three-fold: 1) Ultra-thin 100 μm glass, 2) Double-side thinfilm RF circuits interconnected with Through-Package Vias (TPVs), and 3) Direct assembly of the glass-core package to the board with Land Grid Array (LGA) connections. An innovative double-via process, starting from prefabricated vias in bare glass, polymer filling and via drilling, is utilized for a robust and high-yield substrate fabrication process. Scalable and low-cost panel laminate processes are utilized to form the RF circuits on the build-up layers. The performance benefits are demonstrated through interconnect loss, impedance match, electrical gain and noise figure measurements. Compared to existing RF substrates, the glass substrates show 2.5X miniaturization in substrate thickness with extensibility to thinner substrates.</P>
-
Kumar, Gokul,Sitaraman, Srikrishna,Jonghyun Cho,Sundaram, Venky,Joungho Kim,Tummala, Rao R. IEEE 2016 IEEE transactions on components, packaging, and ma Vol.6 No.1
<P>Ultrathin 3-D glass interposers with throughpackage vias at the same pitch as through-silicon vias (TSVs) have been proposed as a simpler and cheaper alternative to the direct 3-D stacking of logic and memory devices. Such 3-D interposers provide wide-I/O channels for high signal bandwidth (BW) between the logic device on one side of the interposer and memory stack on the other side, without the use of complex TSVs in the logic die. However, this configuration introduces power delivery design challenges due to resonance from: 1) the low-loss property of the glass substrate and 2) the parasitic inductance due to additional length from lateral power delivery path. This paper presents for the first time, the design and demonstration of power delivery networks (PDNs) in 30-μm thin, 3-D double-sided glass interposers, by suppressing the noise from mode resonances. The self-impedance of the 3-D glass interposer PDN was simulated using electromagnetic solvers, including printed-wiring-board and chip-level models. The 3-D PDN was compared with that of the 2-D glass packages having fully populated ball grid array connections. The resonance mechanism for each configuration was studied in detail, and the corresponding PDN loop inductances were evaluated. High impedance peaks in addition to the 2-D PDN were observed at high frequencies (near 7.3 GHz) in the 3-D interposer structure due to the increased inductances from lateral power delivery. This paper proposes and evaluates three important resonance suppression techniques based on: 1) 3-D interposer die configuration; 2) the selection and placement of decoupling capacitors; and 3) 3-D interposer package power and ground stack-up. Two-metal and four-metal layer test vehicles were fabricated on 30and 100-μm thick panel-based glass substrates, respectively, to validate the modeling and analysis of the proposed approach. The PDN test structures were characterized up to 20 GHz for plane resonances and network impedances, with good model-to-hardware correlation. The results in this paper suggest that the ultrathin 3-D interposer PDN structure can be effectively designed to meet the target impedance guidelines for high-BW applications, providing a compelling alternative to 3-D-IC stacking with the TSVs.</P>
-
진상훈,윤영,조유근,이상율,HyungSoo Moon,Seongho Seok,김명준,김재정,이민형 한국공업화학회 2021 Journal of Industrial and Engineering Chemistry Vol.96 No.-
Through-glass vias (TGVs) have been extensively researched due to the unique properties of glass,including low dielectric constant, high transparency, high mechanical, thermal and chemical resistance,and low cost. The TGVs are typicallyfilled with Cu by electrodeposition to make electrical connections inhigh-performance electronics with 3D integration. The Cu electrodeposition process employed tofill thethrough-holes is similar to the one used for printed circuit boards (PCBs), and defect-free Cu can beachieved with a butterflyfilling mechanism. This study introduces the defect-free Cufilling of TGVs usingpolyvinylpyrrolidone (PVP) as a leveler. The effects of PVP molecular weight on the formation ofsuppression layers on the Cu surface was examined by electrochemical analyses. It was found that thesmaller PVP (10,000 g/mol) was beneficial, forming a more compact suppression layer. In contrast, thelayer of larger PVPs (360,000 g/mol) contained a large number of defects where the accelerator couldadsorb, resulting in conformal electrodeposition. As a result, the PVP with a molecular weight of 10,000 g/mol led to defect-free butterflyfilling at TGVs with increasing thefilling performance by 20% compared tothe larger PVP.
-
석범창,정재필 대한용접접합학회 2024 대한용접·접합학회지 Vol.42 No.2
In recent semiconductor packaging, the adoption of through silicon via (TSV) technology has become crucial for the integration of 2.5 and 3D Si chips, and interposers. The TSV offers significant advantages including high interconnect density, shortened signal pathways, and improved electrical performance. However, challenges such as electrical loss, substrate warpage, and high manufacturing costs are associated with TSV implementation. In contrast, glass-based through-glass vias (TGVs) exhibit promising characteristics such as excellent insulation properties, cost-effectiveness, and variable coefficient of thermal expansion (CTE) values that mitigate warpage in stacked devices. Moreover, they facilitate miniaturization and support high-frequency applications. This paper provides an overview of recent advancements in glass substrate, TGV drilling techniques, functional layer depositions, and Cu-filling processes in semiconductor packaging evolution.
-
TGV 인터포저의 디싱 제어를 위한 2-step CMP 전략
정승훈,신영일,정종민,정선호,정해도 한국정밀공학회 2024 한국정밀공학회지 Vol.41 No.6
Chemical mechanical planarization (CMP) is an essential polishing process in semiconductor manufacturing. Advancesin memory technology, including increased capacity and performance, have increased the importance of electronicpackaging. In heterogeneous integration, the interposer acts as an important intermediary between the logic die andthe substrate, solving numerous I/O bump problems in high-bandwidth memory (HBM) and logic chips. Traditionally,board-to-memory connections were made through wire bonding, which required additional space for wire connectionsand introduced latency due to extended signal transmission paths. A through-type approach has emerged as asolution that can significantly reduce waiting time and installation space by improving space efficiency and enablingvertical connections without extending wiring. Due to these new approaches, the importance of CMP is reemerging. Implementation of this important process requires precise control of the CMP dishing/extrusion of bonding surfaces. Improper selection of Cu pad dishing/protrusion can cause problems such as increased RC delay time and signalshort circuit in the wiring. In this paper, we proposed a strategy to control dishing using CMP, especially for Throughglass-via (TGV).
-
-
-
-
DBpia연관 검색어 추천
이 검색어로 많이 본 자료
활용도 높은 자료
