전기차 동력전달계 실험장치의 가상공학설계

김정윤 ( Jung Yun Kim ),권태우 ( Taewoo Kwon ) 대구가톨릭대학교 자연과학연구소 2015 자연과학연구논문집 Vol.13 No.1

The vehicle powertrain testbench is generally developed in order to predict and analyze the driving performance of a vehicle. Therefore it is important to consider various driving conditions and feasible powertrain structures at the design stage of a powertrain testbench. However it is difficult to design and prototype the testbench which includes the above design elements in practice. In order to resolve this problem, this paper describes the virtual design of a powertrain testbench using ADAMS software, which can simulate and analyze dynamic mechanical systems. Using ADAMS software, the main components and structures of the powertrain testbench are virtually designed and validated prior to the hardware implementation. And the various driving conditions of the testbench can be simulated and analyzed in virtual test environment to enhance its feasibility and usefulness.

FPGA기반 원전용 제어기 코드커버리지 개선

허형석,오승록,김규철,Heo, Hyung-Suk,Oh, Seungrohk,Kim, Kyuchull 한국전기전자학회 2014 전기전자학회논문지 Vol.18 No.3

기존의 Verilog테스트벤치로 원전용 안정등급 제어기기와 같이 복잡하고 높은 신뢰도를 요구하는 모듈의 테스트는 수작업으로만 수행된 결과를 가지고 RTL단계의 검증을 마무리하기에는 현실적으로 많은 시간과 노력이 필요하다. UVM은 기존의 테스트벤치의 한계점을 보완하는 계층적 테스트벤치의 구조를 갖고 있어 DUT의 검증을 위한 테스트개선에 대해 테스트벤치의 수정을 간편하게 할 수 있다. 비록 구축과정이 다소 복잡하긴 하지만 테스트 벤치의 컴포넌트들인 driver나 sequence 등을 사용함으로 constraint random test를 가능하게 하여 test vector 작성을 편리하게 한다. 본 논문에서는 기존의 테스트벤치와 계층적 테스트벤치인 UVM테스트벤치를 사용하여 실제 시뮬레이션 하고 커버리지를 분석하여 코드커버리지를 간편하게 향상 할 수 있음을 보였다. IIt takes a lot of time and needs the workloads to verify the RTL code used in complex system like a nuclear control system which is required high level reliability using simple testbench. UVM has a layered testbench architecture and it is easy to modify the testbench to improve the code coverage. A test vector can be easily constructed in the UVM, since a constrained random test vector can be used even though the construction of testbench using UVM. We showed that the UVM testbench is easier than the verilog testbench for the analysis and improvement of code coverage.

Implementation of a Layered Testbench using SystemVerilog

Byeong-Deok Kim,Young-Jin Oh,Myoung-Keun You,Gi-Yong Song 대한전자공학회 2009 ITC-CSCC :International Technical Conference on Ci Vol.2009 No.7

This paper describes functional verification on adaptive FIR filter using SystemVerilog. SystemVerilog has characteristics of hardware description languages and hardware verification language by expansion of Verilog HDL. Adaptive filter is a kind of FIR filter using adaptive algorithm. In this paper, testbench-based verification environment which verifies the functionality of adaptive FIR filter has a layered structure and is implemented with SystemVerilog.

계층화된 테스트벤치를 이용한 검증 환경 구현

오영진,송기용,Oh, Young-Jin,Song, Gi-Yong 한국융합신호처리학회 2011 융합신호처리학회 논문지 (JISPS) Vol.12 No.2

최근 시스템의 규모가 커지고 복잡해지면서, 시스템 수준에서의 기능 검증방법론이 중요해지고 있다. 기능블록의 검증을 위해서는 주로 BFM(bus functional model)이 사용되며, 기능 검증에 대한 부담이 증가할수록 올바른 검증환경 구성의 중요성은 더욱 증가한다. SystemVerilog는 Verilog HDL의 확장으로 하드웨어 설계언어의 특징과 검증언어의 특징을 동시에 갖는다. 동일한 언어로 설계기술, 기능 시뮬레이션 그리고 검증을 진행할 수 있다는 것은 시스템개발에서 큰 이점을 갖는다. 본 논문에서는 SystemVerilog를 이용하여 AMBA 버스와 기능블록으로 구성된 DUT를 설계하고, 계층적 테스트벤치를 이용한 검증환경에서 DUT의 가능을 검증한다. 기능 블록은 Adaptive FIR 필터와 Booth's 곱셈기를 사용한다. 이를 통하여 검증환경이 DUT와 연결되는 인터페이스의 부분적인 변경을 통하여 다른 하드웨어의 기능을 검증하는데 재사용되는 이점을 가지고 있음을 확인한다. Recently, as the design of a system gets larger and more complex, functional verification method based on system-level becomes more important. The verification of a functional block mainly uses BFM(bus functional model). The larger the burden on functional verification is, the more the importance of configuring a proper verification environment increases rapidly. SystemVerilog unifies hardware design languages and verification languages in the form of extensions to the Veri log HDL. The processing of design description, function simulation and verification using same language has many advantages in system development. In this paper, we design DUT that is composed of AMBA bus and function blocks using SystemVerilog and verify the function of DUT in verification environment using layered testbench. Adaptive FIR filter and Booth's multiplier are chosen as function blocks. We confirm that verification environment can be reused through a minor adaptation of interface to verify functions of other DUT.

Testbench Implementation for FPGA based Nuclear Safety Class System using OVM

Heo, Hyung-Suk,Oh, Seungrohk,Kim, Kyuchull Institute of Korean Electrical and Electronics Eng 2014 전기전자학회논문지 Vol.18 No.4

A safety class field programmable gate array based system in nuclear power plant has been developed to improve the diversity. Testbench is necessary to satisfy the technical reference, IEC-62566, for verification and validation of register transfer level code. We use the open verification methodology(OVM) developed by standard body. We show that our testbench can use random input for test. And also we show that reusability of block level testbench for the integration level testbench, which is very efficient for large scale system like nuclear reactor protection system.

Testbench Implementation for FPGA based Nuclear Safety Class System using OVM

허형석,오승록,김규철 한국전기전자학회 2014 전기전자학회논문지 Vol.18 No.4

A safety class field programmable gate array based system in nuclear power plant has been developed to improve the diversity. Testbench is necessary to satisfy the technical reference, IEC-62566, for verification and validation of register transfer level code. We use the open verification methodology(OVM) developed by standard body. We show that our testbench can use random input for test. And also we show that reusability of block level testbench for the integration level testbench, which is very efficient for large scale system like nuclear reactor protection system.

SystemVerilog와 SystemC 기반의 통합검증환경 설계 및 구현

유명근,송기용,You, Myoung-Keun,Song, Gi-Yong 한국융합신호처리학회 2009 융합신호처리학회 논문지 (JISPS) Vol.10 No.4

시스템수준 설계방법론에서 널리 사용하고 있는 설계흐름도는 시스템명세, 시스템수준의 HW/SW 분할, HW/SW 통합설계, 가상 또는 물리적 프로토타입을 이용한 통합검증, 시스템통합으로 구성된다. 본 논문에서는 SystemVerilog와 SystemC를 기반으로 하여 신속한 기능검증이 가능한 native-code 통합검증환경과 클럭수준 검증까지 가능한 계층화 통합검증환경을 각각 구현하였다. Native-code 통합검증환경은 시스템수준 설계언어인 SystemC를 이용하여 HW/SW 분할단계를 수행한 후, SoC 설계의 HW부분과 SW부분을 각각 SystemVerilog와 SystemC로 모델링하여 상호작용을 하나의 시뮬레이션 프로세스로 검증한다. 계층화된 SystemVerilog 테스트벤치는 임의의 테스트벡터를 생성하여 DUT의 모서리 시험을 포함하는 검증환경으로 본 논문에서는 SystemC를 도입하여 다중 상속을 가지는 통합검증환경의 구성요소를 먼저 설계한 후, SystemVerilog DPI와 ModelSim 매크로를 이용하여 SystemVerilog 테스트벤치와 결합된 통합검증환경을 설계한다. 다중 상속은 여러 기초클래스를 결합한 새로운 클래스를 정의하여 코드의 재사용성을 높이는 장점을 가지므로, 본 논문의 SystemC를 도입한 통합검증환경 설계는 검증된 기존의 코드를 재사용할 수 있는 이점을 가진다. The flow of a universal system-level design methodology consists of system specification, system-level hardware/software partitioning, co-design, co-verification using virtual or physical prototype, and system integration. In this paper, verification environments based-on SystemVerilog and SystemC, one is native-code co-verification environment which makes prompt functional verification possible and another is SystemVerilog layered testbench which makes clock-level verification possible, are implemented. In native-code co-verification, HW and SW parts of SoC are respectively designed with SystemVerilog and SystemC after HW/SW partitioning using SystemC, then the functional interaction between HW and SW parts is carried out as one simulation process. SystemVerilog layered testbench is a verification environment including corner case test of DUT through the randomly generated test-vector. We adopt SystemC to design a component of verification environment which has multiple inheritance, and we combine SystemC design unit with the SystemVerilog layered testbench using SystemVerilog DPI and ModelSim macro. As multiple inheritance is useful for creating class types that combine the properties of two or more class types, the design of verification environment adopting SystemC in this paper can increase the code reusability.

A Study on Fuel Injector Testbench for Heavy Duty Engine

Shubhra Kanti Das,Sakda Thongchai(삭다),Ocktaeck Lim(임옥택),Sangjin Yoon 한국자동차공학회 2015 한국자동차공학회 학술대회 및 전시회 Vol.2015 No.11

SystemVerilog-Based Verification Environment Employing Multiple Inheritance of SystemC

YOU, Myoung-Keun,SONG, Gi-Yong The Institute of Electronics, Information and Comm 2010 IEICE transactions on fundamentals of electronics, Vol.93 No.5

<P>In this paper, we describe a verification environment which is based on a constrained random layered testbench using SystemVerilog OOP. As SystemVerilog OOP technique does not allow multiple inheritance, we adopt SystemC to design components of a verification environment which employ multiple inheritance. Then SystemC design unit is linked to a SystemVerilog-based verification environment using SystemVerilog DPI and ModelSim macro. Employing multiple inheritance of SystemC makes the design phase of verification environment simple and easy through source code reusability without corruption due to multi-level single inheritance.</P>

System-Level Verification Platform using SystemVerilog Layered Testbench & SystemC OOP

Young-Jin Oh,Gi-Yong Song 보안공학연구지원센터 2014 International Journal of Control and Automation Vol.7 No.2