Fine-pitch 소자 적용을 위한 bumpless 배선 시스템

김사라은경,Kim, Sarah Eunkyung 한국마이크로전자및패키징학회 2014 마이크로전자 및 패키징학회지 Vol.21 No.3

차세대 전자소자는 입출력(I/O) 핀 수의 증가, 전력소모의 감소, 소형화 등으로 인해 fine-pitch 배선 시스템이 요구되고 있다. Fine-pitch 특히 10 um 이하의 fine-pitch에서는 기존의 무연솔더나 Cu pillar/solder cap 구조를 사용할 수 없기 때문에 Cu-to-Cu bumpless 배선 시스템은 2D/3D 소자 구조에서 매우 필요한 기술이라 하겠다. Bumpless 배선 기술로는 BBUL 기술, 접착제를 이용한 WOW의 본딩 기술, SAB 기술, SAM 기술, 그리고 Cu-to-Cu 열압착 본딩 기술 등이 연구되고 있다. Fine-pitch Cu-to-Cu interconnect 기술은 연결 방법에 상관없이 Cu 층의 불순물을 제거하는 표면 처리 공정, 표면 활성화, 표면 평탄도 및 거칠기가 매우 중요한 요소라 하겠다. The demand for fine-pitch devices is increasing due to an increase in I/O pin count, a reduction in power consumption, and a miniaturization of chip and package. In addition non-scalability of Cu pillar/Sn cap or Pb-free solder structure for fine-pitch interconnection leads to the development of bumpless interconnection system. Few bumpless interconnect systems such as BBUL technology, SAB technology, SAM technology, Cu-toCu thermocompression technology, and WOW's bumpless technology using an adhesive have been reviewed in this paper: The key requirements for Cu bumpless technology are the planarization, contamination-free surface, and surface activation.

Fine-Pitch Solder on Pad Process for Microbump Interconnection

배현철,이학선,최광성,엄용성 한국전자통신연구원 2013 ETRI Journal Vol.35 No.6

A cost-effective and simple solder on pad (SoP) process is proposed for a fine-pitch microbump interconnection. A novel solder bump maker (SBM) material is applied to form a 60-μm pitch SoP. SBM, which is composed of ternary Sn3.0Ag0.5Cu (SAC305) solder powder and a polymer resin, is a paste material used to perform a fine-pitch SoP through a screen printing method. By optimizing the volumetric ratio of the resin, deoxidizing agent, and SAC305 solder powder, the oxide layers on the solder powder and Cu pads are successfully removed during the bumping process without additional treatment or equipment. Test vehicles with a daisy chain pattern are fabricated to develop the fine-pitch SoP process and evaluate the fine-pitch interconnection. The fabricated Si chip has 6,724 bumps with a 45-μm diameter and 60-μm pitch. The chip is flip chip bonded with a Si substrate using an underfill material with fluxing features. Using the fluxing underfill material is advantageous since it eliminates the flux cleaning process and capillary flow process of the underfill. The optimized bonding process is validated through an electrical characterization of the daisy chain pattern. This work is the first report on a successful operation of a fine-pitch SoP and microbump interconnection using a screen printing process.

Novel Low-Volume Solder-on-Pad Process for Fine Pitch Cu Pillar Bump Interconnection

Bae, Hyun-Cheol,Lee, Haksun,Eom, Yong-Sung,Choi, Kwang-Seong The Korean Microelectronics and Packaging Society 2015 마이크로전자 및 패키징학회지 Vol.22 No.2

Novel low-volume solder-on-pad (SoP) process is proposed for a fine pitch Cu pillar bump interconnection. A novel solder bumping material (SBM) has been developed for the $60{\mu}m$ pitch SoP using screen printing process. SBM, which is composed of ternary Sn-3.0Ag-0.5Cu (SAC305) solder powder and a polymer resin, is a paste material to perform a fine-pitch SoP in place of the electroplating process. By optimizing the volumetric ratio of the resin, deoxidizing agent, and SAC305 solder powder; the oxide layers on the solder powder and Cu pads are successfully removed during the bumping process without additional treatment or equipment. The Si chip and substrate with daisy-chain pattern are fabricated to develop the fine pitch SoP process and evaluate the fine-pitch interconnection. The fabricated Si substrate has 6724 under bump metallization (UBM) with a $45{\mu}m$ diameter and $60{\mu}m$ pitch. The Si chip with Cu pillar bump is flip chip bonded with the SoP formed substrate using an underfill material with fluxing features. Using the fluxing underfill material is advantageous since it eliminates the flux cleaning process and capillary flow process of underfill. The optimized interconnection process has been validated by the electrical characterization of the daisy-chain pattern. This work is the first report on a successful operation of a fine-pitch SoP and micro bump interconnection using a screen printing process.

HV-SoP Technology for Maskless Fine-Pitch Bumping Process

손지혜,엄용성,최광성,이학선,배현철,이진호 한국전자통신연구원 2015 ETRI Journal Vol.37 No.3

Recently, we have witnessed the gradual miniaturization of electronic devices. In miniaturized devices, flip-chip bonding has become a necessity over other bonding methods. For the electrical connections in miniaturized devices, fine-pitch solder bumping has been widely studied. In this study, high-volume solder-on-pad (HV-SoP) technology was developed using a novel maskless printing method. For the new SoP process, we used a special material called a solder bump maker (SBM). Using an SBM, which consists of resin and solder powder, uniform bumps can easily be made without a mask. To optimize the height of solder bumps, various conditions such as the mask design, oxygen concentration, and processing method are controlled. In this study, a double printing method, which is a modification of a general single printing method, is suggested. The average, maximum, and minimum obtained heights of solder bumps are 28.3 μm, 31.7 μm, and 26.3 μm, respectively. It is expected that the HV-SoP process will reduce the costs for solder bumping and will be used for electrical interconnections in fine-pitch flip-chip bonding.

Scaling effects of a fine-pitched and vertically guided MEMS probe card

Likun Zhu,Bong-Hwan Kim,Ki Sung Lee,Byeungleul Lee,Kukjin Chun 대한전자공학회 2009 ITC-CSCC :International Technical Conference on Ci Vol.2009 No.7

In this paper, we proposed scaling of MEMS probe card which was developed with a fine-pitched and vertically guided probe structure. The probe structure was mechanically stable and movable only for vertical direction due to a deeply recessed trench. We also considered fabrication limitations such as through-hole etching, electroplating, and planarization of wafer for implement a fine-pitched device.

새로운 구조의 동축 테스트 소켓을 이용한 미세 피치 프로브 핀의 신호 전달 특성 개선

김문정,서정준 한국반도체디스플레이기술학회 2024 반도체디스플레이기술학회지 Vol.23 No.1

In this paper, the difference between the S-parameter and the characteristic impedance according to the structural change of the fine pitch coaxial socket was analyzed. A pitch of the probe pin was applied to 0.20mm, and ground pins of different conditions were placed on each of the five signal pins. Insertion loss and reflection loss were analyzed for the coaxial socket of normal structure and the two sockets of the proposed structure. In addition, the difference in characteristic impedance was analyzed using time domain reflectometry. Through the analysis, it was confirmed that the characteristic impedance was improved applying the new structures of the socket at the same pitch.

Optimization of Material and Process for Fine Pitch LVSoP Technology

엄용성,손지혜,배현철,최광성,최흥섭 한국전자통신연구원 2013 ETRI Journal Vol.35 No.4

For the formation of solder bumps with a fine pitch of 130 μm on a printed circuit board substrate, low-volume solder on pad (LVSoP) technology using a maskless method is developed for SAC305 solder with a high melting temperature of 220°C. The solder bump maker (SBM) paste and its process are quantitatively optimized to obtain a uniform solder bump height, which is almost equal to the height of the solder resist. For an understanding of chemorheological phenomena of SBM paste, differential scanning calorimetry, viscosity measurement, and physical flowing of SBM paste are precisely characterized and observed during LVSoP processing. The average height of the solder bumps and their maximum and minimum values are 14.7 μm, 18.3 μm, and 12.0 μm, respectively. It is expected that maskless LVSoP technology can be effectively used for a fine-pitch interconnection of a Cu pillar in the semiconductor packaging field.

미세피치 패키지 적용을 위한 thin ENEPIG 도금층의 솔더링 특성

백종훈,이병석,유세훈,한덕곤,정승부,윤정원,Back, Jong-Hoon,Lee, Byung-Suk,Yoo, Sehoon,Han, Deok-Gon,Jung, Seung-Boo,Yoon, Jeong-Won 한국마이크로전자및패키징학회 2017 마이크로전자 및 패키징학회지 Vol.24 No.1

본 연구에서는 미세피치 패키지 적용을 위한 기초 실험으로 thin ENEPIG(Electroless Nickel Electroless Palladium Immersion Gold) 도금층을 형성하여 솔더링 특성을 평가하였다. 먼저, Sn-3.0Ag-0.5Cu (SAC305) 솔더합금에 대한 thin ENEPIG 도금층의 젖음 특성이 평가되었으며, 순차적인 솔더와의 반응에 대한 계면반응 및 솔더볼 접합 후 고속 전단 시험을 통한 접합부 기계적 신뢰성이 평가되었다. 젖음성 시험에서 침지 시간이 증가함에 따라 최대 젖음력은 증가하였으며, 5초의 침지 시간 이후에는 최대 젖음력이 일정하게 유지되었다. 초기 계면 반응 동안에는 $(Cu,Ni)_6Sn_5$ 금속간화합물과 P-rich Ni 층이 SAC305/ENEPIG 계면에서 관찰되었다. 연장된 계면반응 후에는 P-rich Ni 층이 파괴 되었으며, 파괴된 P-rich Ni 층 아래에는 $(Cu,Ni)_3Sn$ 금속간화합물이 생성되었다. 고속 전단 시험의 경우, 전단속도가 증가함에 따라 취성 파괴율이 증가하였다. In this paper, we evaluated the solderability of thin electroless nickel-electroless palladium-immersion gold (ENEPIG) plating layer for fine-pitch package applications. Firstly, the wetting behavior, interfacial reactions, and mechanical reliability of a Sn-3.0Ag-0.5Cu (SAC305) solder alloy on a thin ENEPIG coated substrate were evaluated. In the wetting test, maximum wetting force increased with increasing immersion time, and the wetting force remained a constant value after 5 s immersion time. In the initial soldering reaction, $(Cu,Ni)_6Sn_5$ intermetallic compound (IMC) and P-rich Ni layer formed at the SAC305/ENEPIG interface. After a prolonged reaction, the P-rich Ni layer was destroyed, and $(Cu,Ni)_3Sn$ IMC formed underneath the destroyed P-rich Ni layer. In the high-speed shear test, the percentage of brittle fracture increased with increasing shear speed.

Sn-3.0Ag-0.5Cu 솔더 접합부의 계면반응과 취성파괴율에 미치는 Thin ENEPIG 도금두께의 영향

백종훈(Jong-Hoon Back),유세훈(Sehoon Yoo),한덕곤(Deok-Gon Han),정승부(Seung-Boo Jung),윤정원(Jeong-Won Yoon) 대한용접·접합학회 2018 대한용접·접합학회지 Vol.36 No.5

In this paper, we evaluated the interfacial reactions and brittle fracture behaviors of thin electroless nickel-electroless palladium-immersion gold (ENEPIG) plating layers with different Ni and Pd thicknesses for fine-pitch package applications. Firstly, the interfacial reactions and mechanical reliability of Sn-3.0Ag-0.5Cu (SAC305)/thin ENEPIG solder joints were evaluated. (Cu,Ni)6Sn5 intermetallic compound (IMC) was formed at all of the thin ENEPIG interfaces, and P-rich Ni layer was also observed at the joint interface of the Pd substrate with 0.3 ㎛ Ni thickness. The interfacial IMC thickness decreased with increasing Ni and Pd thicknesses. In addition, the IMC thickness was affected by the contents of the Pd plating layer. The IMC thickness for the Pd-P substrate was thicker than that for the Pd substrate. In the high-speed shear test, the brittle fracture rate decreased with increasing Ni and Pd thickness. Also, the brittle fracture rate was affected by the components of the Pd plating layer, and the brittle fracture rate for the Pd substrate was lower than that for the Pd-P substrate. The ENEPIG joint with thicker Ni plating layer had superior interfacial stability and mechanical reliability.

미세피치용 Cu/SnAg 더블 범프 플립칩 어셈블리의 신뢰성에 관한 연구

손호영,김일호,이순복,정기조,박병진,백경욱,Son, Ho-Young,Kim, Il-Ho,Lee, Soon-Bok,Jung, Gi-Jo,Park, Byung-Jin,Paik, Kyung-Wook 한국마이크로전자및패키징학회 2008 마이크로전자 및 패키징학회지 Vol.15 No.2

본 논문에서는 유기 기판 위에 $100{\mu}m$ 피치를 갖는 플립칩 구조인 Cu(60 um)/SnAg(20 um) 더블 범프 플립칩 어셈블리를 구현하여 이의 리플로우, 고온 유지 신뢰성, 열주기 신뢰성, Electromigration 신뢰성을 평가하였다. 먼저, 리플로우의 경우 횟수와 온도에 상관없이 범프 접속 저항의 변화는 거의 나타나지 않음을 알 수 있었다. 125도 고온 유지 시험에서는 2000시간까지 접속 저항 변화가 관찰되지 않았던 반면, 150도에서는 Kirkendall void의 형성으로 인한 접속 저항의 증가가 관찰되었다 또한 Electromigration 시험에서는 600시간까지 불량이 발생하지 않았는데 이는 Al금속 배선에서 유발되는 높은 전류 밀도가 Cu 칼럼의 높은 두께로 인해 솔더 영역에서는 낮아지기 때문으로 해석되었다. 열주기 시험의 경우, 400 cycle 이후부터 접속 저항의 증가가 발견되었으며, 이는 열주기 시험 동안 실리콘 칩과 Cu 칼럼 사이에 작용하는 압축 변형에 의해 그 사이에 있는 Al 및 Ti 층이 바깥쪽으로 밀려나감으로 인해 발생하는 것으로 확인되었다. In this study, reliabilities of Cu (60 um)/SnAg (20 um) double-bump flip chip assemblies were investigated for the flip chip interconnections on organic substrates with 100 um pitch. After multiple reflows at $250^{\circ}C\;and\;280^{\circ}C$, bump contact resistances were almost same regardless of number of reflows and reflow temperature. In the high temperature storage test, there was no bump contact resistance change at $125^{\circ}C$ up to 2000 hours. However, bump contact resistances slightly increased at $150^{\circ}C$ due to Kirkendall voids formation. In the electromigration test, Cu/SnAg double-bump flip chip assemblies showed no electromigration until about 600 hours due to reduced local current density. Finally, in the thermal cycling test, thermal cycling failure mainly occurred at Si chip/Cu column interface which was found out the highest stress concentration site in the finite element analysis. As a result, Al pad was displaced out under thermal cycling. This failure mode was caused by normal compressive strain acting Cu column bumps along perpendicular direction of a Si chip.