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UHF RFID 태그 칩용 저전력, 저면적 비동기식 EEPROM 설계
백승면,이재형,송성영,김종희,박문훈,하판봉,김영희,Baek, Seung-Myun,Lee, Jae-Hyung,Song, Sung-Young,Kim, Jong-Hee,Park, Mu-Hun,Ha, Pan-Bong,Kim, Young-Hee 한국정보통신학회 2007 한국정보통신학회논문지 Vol.11 No.12
본 논문에서는 $0.18{\mu}m$의 EEPROM cell을 사용하여 수동형 UHF RFID 태그 칩에 사용되는 저전력, 저면적의 1Kbits 비동기식 EEPROM IP를 설계하였다. 저면적 회로 설계 기술로는 $0.18{\mu}m$ EEPROM 공정을 이용하여 비동기식 EEPROM IP를 설계하므로 command buffer와 address buffer를 제거하였고 separate I/O 방식을 사용하므로 tri-state 데이터 출력 버퍼(data output buffer)를 제거하였다. 그리고 저전압(low voltage)의 VDD에서 EEPROM cell이 필요로 하는 고전압(high voltage)인 VPP와 VPPL 전압을 안정적으로 공급하기 위해 기존의 PN 접합 다이오드 대신 Schottky 다이오드를 사용한 Dickson 전하펌프를 설계하므로 전하펌프의 펌핑단(pumping stage)의 수를 줄여 전하펌프가 차지하는 면적을 줄였다. 저전력 회로 설계 기술로 Dickson 전하 펌프(charge pump)를 이용하여 VPP generator를 만들고 Dickson 전하펌프의 임의의 노드 전압을 이용하여 프로그램과 지우기 모드에서 각각 필요로 하는 VPPL 전압을 선택하도록 하게 해주는 VPPL 전원 스위칭 회로를 제안하여 쓰기전류(write current)를 줄이므로 저전력 EEPROM IP를 구현하였다. $0.18{\mu}m$ 공정을 이용하여 설계된 비동기식 EEPROM용 테스트 칩은 제작 중에 있으며, 비동기식 1Kbits EEPROM의 레이아웃 면적은 $554.8{\times}306.9{\mu}m2$로 동기식 1Kbits EEPROM에 비해 레이아웃면적을 11% 정도 줄였다. In this paper, a low-power and small-area asynchronous 1 kilobit EEPROM for passive UHF RFID tag chips is designed with $0.18{\mu}m$ EEPROM cells. As small area solutions, command and address buffers are removed since we design asynchronous I/O interface and data output buffer is also removed by using separate I/O. To supply stably high voltages VPP and VPPL used in the cell array from low voltage VDD, Dickson charge pump is designed with schottky diodes instead of a PN junction diodes. On that account, we can decrease the number of stages of the charge pump, which can decrease layout area of charge pump. As a low-power solution, we can reduce write current by using the proposed VPPL power switching circuit which selects each needed voltage at either program or write mode. A test chip of asynchronous 1 kilobit EEPROM is fabricated, and its layout area is $554.8{\times}306.9{\mu}m2$., 11% smaller than its synchronous counterpart.
A New Capacitive Sensing Circuit using Modified Charge Transfer Scheme
Yeo, Hyeop-Goo The Korea Institute of Information and Commucation 2011 Journal of information and communication convergen Vol.9 No.1
This paper proposes a new circuit for capacitive sensing based on Dickson's charge pump. The proposed touch sensing circuit includes three stages of NMOS diodes and capacitors for charge transfer. The proposed circuit which has a simplified capacitive touch sensor model has been analyzed and simulated by Spectre using Magna EDMOS technology. Looking from the simulation results, the proposed circuit can effectively be used as a capacitive touch sensing circuit. Moreover, a simple structure can provide maximum flexibility for making a digitally-controlled touch sensor driver with lowpower operations.
Dickson Charge Pump with Gate Drive Enhancement and Area Saving
Hesheng Lin,Wing Chun Chan,Wai Kwong Lee,Zhirong Chen,Min Zhang 전력전자학회 2016 JOURNAL OF POWER ELECTRONICS Vol.16 No.3
This paper presents a novel charge pump scheme that combines the advantages of Fibonacci and Dickson charge pumps to obtain 30 V voltage for display driver integrated circuit application. This design only requires four external capacitors, which is suitable for a small-package application, such as smart card displays. High-amplitude (<6.6 V) clocks are produced to enhance the gate drive of a Dickson charge pump and improve the system’s current drivability by using a voltage-doubler charge pump with a pulse skip regulator. This regulation engages many middle-voltage devices, and approximately 30% of chip size is saved. Further optimization of flying capacitors tends to decrease the total chip size by 2.1%. A precise and simple model for a one-stage Fibonacci charge pump with current load is also proposed for further efficiency optimization. In a practical design, its voltage error is within 0.12% for 1 mA of current load, and it maintains a 2.83% error even for 10 mA of current load. This charge pump is fabricated through a 0.11 μm 1.5 V/6 V/32 V process, and two regulators, namely, a pulse skip one and a linear one, are operated to maintain the output of the charge pump at 30 V. The performances of the two regulators in terms of ripple, efficiency, line regulation, and load regulation are investigated.
Dickson Charge Pump with Gate Drive Enhancement and Area Saving
Lin, Hesheng,Chan, Wing Chun,Lee, Wai Kwong,Chen, Zhirong,Zhang, Min The Korean Institute of Power Electronics 2016 JOURNAL OF POWER ELECTRONICS Vol.16 No.3
This paper presents a novel charge pump scheme that combines the advantages of Fibonacci and Dickson charge pumps to obtain 30 V voltage for display driver integrated circuit application. This design only requires four external capacitors, which is suitable for a small-package application, such as smart card displays. High-amplitude (<6.6 V) clocks are produced to enhance the gate drive of a Dickson charge pump and improve the system's current drivability by using a voltage-doubler charge pump with a pulse skip regulator. This regulation engages many middle-voltage devices, and approximately 30% of chip size is saved. Further optimization of flying capacitors tends to decrease the total chip size by 2.1%. A precise and simple model for a one-stage Fibonacci charge pump with current load is also proposed for further efficiency optimization. In a practical design, its voltage error is within 0.12% for 1 mA of current load, and it maintains a 2.83% error even for 10 mA of current load. This charge pump is fabricated through a 0.11 μm 1.5 V/6 V/32 V process, and two regulators, namely, a pulse skip one and a linear one, are operated to maintain the output of the charge pump at 30 V. The performances of the two regulators in terms of ripple, efficiency, line regulation, and load regulation are investigated.
이중 편파 RF 에너지 하베스팅 시스템을 위한 최적 정류 회로 설계
박정수(Jeong-Su Park),이왕상(Wang-Sang Lee) 대한전기학회 2021 전기학회논문지 Vol.70 No.2
In this paper, a optimal rectifier circuit for dual-polarized RF energy harvesting system operating at 2.45 GHz is proposed. RF power incident from a dual-polarized antenna is converted to DC using individual Dickson charge pump rectifier circuits. According to the series or parallel-connected rectifier circuit with multiple stages, the harvesting voltage and its rectifying efficiency are analyzed and measured. From the experimental verification, the number of stages of the dickson charge pump and the output power according to the series and parallel connections of DC output were compared. The parallel two-stage circuit for dual-polarized RF energy harvesting achieved a maximum voltage of 1.35 V and a power of 0.91 mW, and a rectifying efficiency of approximately 20%.
권승탁,문하영,이계철 한국기계기술학회 2013 한국기계기술학회지 Vol.15 No.6
In this paper, we present a CMOS voltage regulator for application in electric device. This works shows that unlike the traditional voltage converter, this regulator can achieve high efficiency with a good step-down voltage ratio. The circuits which are implemented in this paper is simulated with LT SPICE tool of computer.