CNTFET 기반 회로 성능의 공정 편차 영향 분석을 위한 정확도 향상 방법

조근호,Cho, Geunho 한국전기전자학회 2018 전기전자학회논문지 Vol.22 No.2

가까운 미래에, 전자의 ballastic 혹은 near-ballastic 이동이 가능한 CNT(Carbon NanoTube)를 활용한 CNTFET(Carbon NanoTube Field Effect Transistor)은 현재의 실리콘 기반 트랜지스터를 교체할 유력한 후보 중 하나로 고려되고 있다. 고성능의 CNTFET으로 대규모 집적회로를 구현하기 위해서는 semiconducting CNT가 CNTFET 안에 동일한 간격과 높은 밀도로 정렬되어 배치되어야 하지만, CNTFET 공정의 미성숙으로, CNTFET 안의 CNT는 불규칙하게 배치하게 되고, 현존하는 HSPICE 라이브러리 파일은 불규칙한 CNT 배치에 의한 성능의 변화를 회로 레벨에서 평가할 수 있는 기능을 지원하지 않는다. 이러한 성능의 변화를 평가하기 위해서 선형 프로그래밍을 활용한 방법이 과거에 제안되었으나, CNTFET의 전류와 게이트 커패시턴스를 계산하는 과정에서 오차가 발생할 수 있는 문제점이 있다. 본 논문에서는 언급한 오차가 발생되는 이유에 대해서 자세히 논하고, 이 오차를 줄일 수 있는 새로운 방법을 제시하고자 한다. 시뮬레이션 검토 결과, 새롭게 제시된 방법이 기존 방법의 오차, 7.096%를 3.15%까지 줄일 수 있음을 보이고 있다. In the near future, CNTFET(Carbon NanoTube Field Effect Transistor) is considered as one of the most promising candidate for the replacement of modern silicon-based transistors by utilizing the ballistic or near-ballistic transport capability of CNT(Carbon NanoTube). For the large-scale fabrication of high performance CNTFET, semiconducting CNTs have to be well-aligned with a fixed pitch and high densities in the each CNTFET. However, due to the immaturity of the CNTFET fabrication process, CNTs can be unevenly positioned in a CNTFET and existing HSPICE library file cannot support the circuit level evaluation of performance variation caused by the unevenly positioned CNTs. To evaluate the performance variation, linear programming methodology was suggested previously, but the errors can be made during the calculation of the current and the gate capacitance of a CNTFET. In this paper, the reasons causing errors will be discussed in detail and the new methodology to reduce the errors will be also suggested. Simulation results shows that the errors can be reduced from 7.096% to 3.15%.

하이브리드 MOSFET-CNTFET 기반 SRAM 디자인 방법에 관한 연구

조근호 한국전기전자학회 2023 전기전자학회논문지 Vol.27 No.1

More than 10,000 Carbon NanoTube Field Effect Transistors (CNTFETs), which have advantages such as highcarrier mobility, large saturation velocity, low intrinsic capacitance, flexibility, and transparency, have beensuccessfully integrated into one semiconductor chip using conventional semiconductor design procedures andmanufacturing processes. Three-dimensional multilayer structure of the CNTFET semiconductor chip and variousCNTFET manufacturing process research increase the possibility of making the hybrid MOSFET-CNTFET semiconductorchip which combines conventional MOSFETs and CNTFETs together in a semiconductor chip. This paper discussesa methodology to design 6T binary SRAM using hybrid MOSFET-CNTFET. By utilizing the existing MOSFET SRAMor CNTFET SRAM design method, we will introduce a method of designing a hybrid MOSFET-CNTFET SRAM andcompare its performance with the conventional MOSFET SRAM and CNTFET SRAM. 높은 캐리어 이동도, 큰 포화 속도, 낮은 고유 정전 용량, 유연성, 그리고 투명성을 장점으로 가진 CNTFET(Carbon NanoTubeField Effect Transistor) 10,000개 이상을 현존하는 반도체 디자인 절차와 공정 프로세서를 활용하여 하나의 반도체 칩에 집적하는데 성공하였다. 제작된 반도체 칩의 3차원 다층 구조와 다양한 CNTFET 생산 공정 연구는 기존 MOSFET과 CNTFET를 하나의반도체 칩에 함께 사용하는 hybrid MOSFET-CNTFET 반도체 칩 제작에 대한 가능성을 보여주고 있다. 본 논문에서는 hybridMOSFET-CNTFET을 활용한 6T binary SRAM을 디자인하는 방법에 대해 논하고자 한다. 기존 MOSFET SRAM 또는 CNTFETSRAM 디자인 방법을 활용하여 hybrid MOSFET-CNTFET SRAM을 디자인 하는 방법을 소개하고 그 성능을 기존 MOSFETSRAM 그리고 CNTFET SRAM과 비교하고자 한다.

탄소나노튜브 부분 밀도 변화에 의한 CNTFET SRAM 성능 변화에 대한 연구

조근호 한국전기전자학회 2022 전기전자학회논문지 Vol.26 No.1

With high performance and wide application, a CNTFET has been attracting a lot of attention as a nextenerationsemiconductor, but the manufacturing process of CNTFET has not been mature enough, which makescommercialization difficult. In order to overcome the imperfections of the CNTFET manufacturing process and toincrease the possibility of commercialization, this paper analyzes the CNTFET SRAM performance variationaccording to the CNTFET partial density change based on the recently reported CNTFET manufacturing process. Through HSPICE circuit simulation analysis using the existing 32nm CNTFET HSPICE library file, transistors whoseperformance variation is less sensitive to partial CNT density are selected among the six transistors constitutingthe SRAM cell and acceptable CNT density range is proposed. As the result of analysis, it is found that when theCNT density of the two transistors connected to the bit line in SRAM cell changed from 6/32nm to 8/32nm, thedeviation of SRAM performance is less than 9% and when the CNT density is less than 5/32nm, the SRAM delayis increased by more than 8 time 높은 성능과 폭넓은 활용성으로 CNTFET은 차세대 반도체로 많은 관심을 받아 왔으나 생산 공정이 아직 충분히 성숙되지 않아상용화에 어려움을 겪어 왔다. 이러한 CNTFET 공정의 불완전성을 극복하고 상용화 가능성을 높이기 위해 본 논문에서는 최근 발표된 CNTFET 공정 내용을 참고하여 CNTFET 부분 밀도 변화에 따른 CNTFET SRAM 성능 변화에 대해 분석하고자 한다. 현존하는 32nm CNTFET HSPICE용 라이브로리 파일을 활용한 HSPICE 회로 시뮬레이션 분석을 통해 SRAM 셀을 구성하는 6개의 트랜지스터 중, CNT 밀도 변화에 대해 성능 변화가 덜 민감한 트랜지스터를 선택하고, 허용되는 CNT 밀도 범위를 제안하였다. 분석결과, SRAM 내 비트라인에 연결된 2개의 트랜지스터의 CNT 밀도가 6/32nm에서 8/32nm로 변경되더라도 SRAM 성능 편차는9% 이하인 것으로 나타나고 CNT 밀도가 5/32nm 미만인 경우 SRAM 지연이 약 8배 이상 증가됨을 알 수 있었다.

Channel and Gate Workfunction-Engineered CNTFETs for Low-Power and High-Speed Logic and Memory Applications

Wei Wang,Hongsong Xu,Zhicheng Huang,Lu Zhang,Huan Wang,Sitao Jiang,Min Xu,Jian Gao 대한전자공학회 2016 Journal of semiconductor technology and science Vol.16 No.1

Carbon Nanotube Field-Effect Transistors (CNTFETs) have been studied as candidates for post Si CMOS owing to the better electrostatic control and high mobility. To enhance the immunity against short - channel effects (SCEs), the novel channel and gate engineered architectures have been proposed to improve CNTFETs performance. This work presents a comprehensive study of the influence of channel and gate engineering on the CNTFET switching, high frequency and circuit level performance of carbon nanotube field-effect transistors (CNTFETs). At device level, the effects of channel and gate engineering on the switching and high frequency characteristics for CNTFET have been theoretically investigated by using a quantum kinetic model. This model is based on two-dimensional non-equilibrium Green’s functions (NEGF) solved self - consistently with Poisson’s equations. It is revealed that hetero -material - gate and lightly doped drain and source CNTFET (HMG - LDDS - CNTFET) structure can significantly reduce leakage current, enhance control ability of the gate on channel, improve the switching speed, and is more suitable for use in low power, high frequency circuits. At circuit level, using the HSPICE with look - up table(LUT) based Verilog - A models, the impact of the channel and gate engineering on basic digital circuits (inverter, static random access memory cell) have been investigated systematically. The performance parameters of circuits have been calculated and the optimum metal gate workfunction combinations of ФM1/ФM2 have been concluded in terms of power consumption, average delay, stability, energy consumption and power - delay product (PDP). In addition, we discuss and compare the CNTFET-based circuit designs of various logic gates, including ternary and binary logic. Simulation results indicate that LDDS - HMG - CNTFET circuits with ternary logic gate design have significantly better performance in comparison with other structures.

Quantum Transport Simulations of CNTFETs: Performance Assessment and Comparison Study with GNRFETs

Wang, Wei,Wang, Huan,Wang, Xueying,Li, Na,Zhu, Changru,Xiao, Guangran,Yang, Xiao,Zhang, Lu,Zhang, Ting The Institute of Electronics and Information Engin 2014 Journal of semiconductor technology and science Vol.14 No.5

In this paper, we explore the electrical properties and high-frequency performance of carbon nanotube field-effect transistors (CNTFETs), based on the non-equilibrium Green's functions (NEGF) solved self - consistently with Poisson's equations. The calculated results show that CNTFETs exhibit superior performance compared with graphene nanoribbon field-effect transistors (GNRFETs), such as better control ability of the gate on the channel, higher drive current with lower subthreshold leakage current, and lower subthreshold-swing (SS). Due to larger band-structure-limited velocity in CNTFETs, ballistic CNTFETs present better high-frequency performance limit than that of Si MOSFETs. The parameter effects of CNTFETs are also investigated. In addition, to enhance the immunity against short - channel effects (SCE), hetero - material - gate CNTFETs (HMG-CNTFETs) have been proposed, and we present a detailed numerical simulation to analyze the performances of scaling down, and conclude that HMG-CNTFETs can meet the ITRS'10 requirements better than CNTs.

Channel and Gate Workfunction-Engineered CNTFETs for Low-Power and High-Speed Logic and Memory Applications

Wang, Wei,Xu, Hongsong,Huang, Zhicheng,Zhang, Lu,Wang, Huan,Jiang, Sitao,Xu, Min,Gao, Jian The Institute of Electronics and Information Engin 2016 Journal of semiconductor technology and science Vol.16 No.1

Carbon Nanotube Field-Effect Transistors (CNTFETs) have been studied as candidates for post Si CMOS owing to the better electrostatic control and high mobility. To enhance the immunity against short - channel effects (SCEs), the novel channel and gate engineered architectures have been proposed to improve CNTFETs performance. This work presents a comprehensive study of the influence of channel and gate engineering on the CNTFET switching, high frequency and circuit level performance of carbon nanotube field-effect transistors (CNTFETs). At device level, the effects of channel and gate engineering on the switching and high frequency characteristics for CNTFET have been theoretically investigated by using a quantum kinetic model. This model is based on two-dimensional non-equilibrium Green's functions (NEGF) solved self - consistently with Poisson's equations. It is revealed that hetero - material - gate and lightly doped drain and source CNTFET (HMG - LDDS - CNTFET) structure can significantly reduce leakage current, enhance control ability of the gate on channel, improve the switching speed, and is more suitable for use in low power, high frequency circuits. At circuit level, using the HSPICE with look - up table(LUT) based Verilog - A models, the impact of the channel and gate engineering on basic digital circuits (inverter, static random access memory cell) have been investigated systematically. The performance parameters of circuits have been calculated and the optimum metal gate workfunction combinations of ${\Phi}_{M1}/{\Phi}_{M2}$ have been concluded in terms of power consumption, average delay, stability, energy consumption and power - delay product (PDP). In addition, we discuss and compare the CNTFET-based circuit designs of various logic gates, including ternary and binary logic. Simulation results indicate that LDDS - HMG - CNTFET circuits with ternary logic gate design have significantly better performance in comparison with other structures.

CNTFET Based Ternary 1-Trit & 2-Trit Comparators for Low Power High-Performance Applications

Suman Rani,Balwinder Singh,Rekha Devi 한국전기전자재료학회 2021 Transactions on Electrical and Electronic Material Vol.22 No.6

1-Trit and 2-Trit Ternary comparator circuits using Complementary Metal–Oxide–Semiconductor (CMOS) as well as Carbon Nanotube Field-Effect Transistor (CNTFET) is proposed and investigated for Low Power High-performance applications. The design and simulation are investigated and authenticated using Hailey Simulation Program with Integrated Circuit (HSPICE) with Predictive technology model (PTM) low power 32 nm metal gate/High-K/Strained-Si Model for CMOS and 32 nm Stanford Model for CNTFET. The CNTFET based design is compared with the CMOS design in terms of signifi cant design aspects, specifically delay, Average Power consumption and Power delay product (PDP). A comparison is performed among CMOS and CNTFET based ternary comparator circuits which reveals that CNTFETs can lead to more efficient ternary circuits. In terms of delay and power consumption, the CNTFET based 1-Trit Ternary Comparator performs better than the CMOS based 1-Trit Ternary Comparator as the delay and Average power consumption are reduced by 89.7% and 57.3% in CNTFET type as compared to the CMOS based 1-Trit Ternary Comparator design. Similarly, in the case of the 2-Trit comparator, the CNTFET based design performs better than the CMOS-based design as the delay and Average power consumption are reduced by 88.7% and 42% in the CNTFET type.

공정 편차가 하이브리드 MOSFET-CNTFET 기반SRAM의 성능에 미치는 영향에 대한 연구

조근호 한국전기전자학회 2023 전기전자학회논문지 Vol.27 No.3

전통적인 실리콘 기반 반도체 소자 보다 높은 성능과 다양한 활용성으로 차세대 반도체 후보로 높은 관심 받고 있는 CNTFET은CNT 배치와 같은 CNTFET만의 고유한 공정 편차가 아직 성숙되지 않아 상용화에 어려움을 겪고 있다. 이러한 어려움을 극복하고자 반복적인 회로 구성으로 공정 편차의 영향을 적게 받는 회로를 MOSFET-CNTFET 기반 하이브리드 회로로 구현하여 CNTFET의 장점을 취하고 단점을 보완하고자 하는 수많은 연구들이 지속적으로 수행되어 왔다. 본 논문에서는 하이브리드 SRAM의 성능이기존의 MOSFET SRAM 또는 CNTFET SRAM에 존재하는 반도체 공정 변화에 의해 얼마나 변화될 수 있는지를 비교하였다. 시뮬레이션 결과, CNT 밀도를 32nm 당 7개에서 9개 사이로 유지할 수 있다면, hybrid SRAM은 기존 MOSFET SRAM보다 읽기 동작에서 그리고 쓰기 동작에서 공정 편차에 대한 강건성이 각각 약 2.6배 그리고 약 1.1배 있음을 보여준다 CNTFET, which is receiving high attention as a next-generation semiconductor candidate due to its higherperformance and various utilization than traditional silicon-based semiconductor devices, is having difficulty incommercialization because its unique process deviation such as CNT placement has not yet matured. To overcomethis difficulty, numerous studies have been continuously conducted to take advantages of CNTFET and compensateits weakness by implementing circuits, which are less affected by process deviation due to repetitive circuitplacement, into MOSFET-CNTFET based hybrid circuits. This paper compares how much the performance of thehybrid SRAM can be changed by semiconductor process variation existing in the traditional MOSFET SRAM orCNTFET SRAM. Simulation results show that, if the CNT density can be maintained between 7 and 9 per 32nm,hybrid SRAM is about 2.6 times and about 1.1 times more robust to process deviation than conventional MOSFETSRAM in read and write operations, respectively.

CNTFET 기반 회로 설계를 위한 공정 편차 분석에 관한 연구

조근호 한국전기전자학회 2018 전기전자학회논문지 Vol.22 No.1

차세대 반도체로 각광받고 있는 CNTFET은 기존 MOSFET의 Source와 Drain 사이에 CNT를 배치하여 그 성능을 향상시킬 수 있는 구조를 가지고 있으나, 다양한 CNT 배치로 인한 CNTFET의 구조적 변화는 소자 성능에 대한 해석의 복잡도를 증가시켜, 공정 편차가 반도체 소자 성능에 미치는 영향을 분석하고자 할 때, 기존의 MOSFET에 비해 보다 많은 계산을 요구하는 문제점을 가지고 있다. 이러한 문제점은 공정편차 분석에 필요한 시뮬레이션 시간을 급격하게 증가시키고 기존 툴(tool)로 분석할 수 없는 경우를 포함하고 있어 CNTFET으로 회로를 디자인 하는데 중요한 걸림돌로 작용하고 있다. 본 연구에서는 시뮬레이션의 급격한 증가를 해결하기 위한 방법으로서 기존 Linear Programming이 활용될 수 있음을 보이고 그 효과에 대해 자세히 논의하고자 한다. 시뮬레이션 결과 CNT 최대 배치 수가 6에서 12까지 증가할 때, Linear Programming 방법은 시뮬레이션 횟수를 약 2.5배 감소시킬 수 있음을 보이고 있다. The CNTFET, which is widely recognized as a next-generation semiconductor, has a structure that can improve performance by positioning CNTs between the source and drain of a conventional MOSFET. However, positioning CNTs increases the complexity of a CNTFET’s structure, and the process variation changes the complex structure into various shapes; so, when CNTFET device performance is analyzed, it requires more computation than that of a conventional MOSFET. These problems greatly increase the simulation time necessary for the analysis, and sometimes that analysis cannot be performed using an existing tool; they are therefore important obstacles to designing a circuit using a CNTFET. In this study, we will show that the existing Linear Programming methodology can be utilized to solve the long simulation time problem and discuss the effect of the suggested method in detail. Simulation results show that the Linear Programming method can reduce the number of simulation about 2.5 times when the maximum number of CNT is changed from 6 to 12.

탄소나노튜브 밀도를 고려한 CNTFET SRAM 디자인 방법에 관한 연구

조근호(Geunho Cho) 한국전기전자학회 2021 전기전자학회논문지 Vol.25 No.3

CNTFET은 기존 반도체 소자의 성능을 약 13배 향상시킬 수 있어 큰 관심을 받아 왔지만, CNT를 일정하게 배치시키는 공정의 미성숙으로 인해 상용화에 어려움을 겪어 왔다. 이러한 어려움을 극복하기 위해, 그동안 알려진 CNTFET 공정상 한계를 고려한 회로 디자인 방법이 점점 높은 관심을 받고 있다. SRAM은 마이크로프로세서를 구성하는 주요 요소로서 캐시메모리 안에 규칙적으로 그리고 반복적으로 배치되어 있어, SRAM 안의 CNT는 다른 회로 블록에 비해 보다 쉽게 그리고 고밀도로 배치될 수 있는 장점이 있다. 이러한 장점을 활용하기 위해, 본 논문에서는 CNT 밀도를 고려한 SRAM 셀의 회로디자인 방법을 소개하고 그 성능 향상 정도를 HSPICE 시뮬레이션으로 검토하고자 한다. 시뮬레이션 결과, SRAM에 CNTFET을 적용할 경우, gate width를 약 1.7배 줄일 수 있음을 발견하였으며, 동일한 gate width에서 CNT 밀도를 높였을 경우, 읽기 속도 또한 약 2배 정도 향상될 수 있음을 알 수 있었다. Although CNTFETs have attracted great attention due to their ability to increase semiconductor device performance by about 13 times, the commercialization of CNTFETs has been challenging because of the immature deposition process of CNTs. To overcome these difficulties, circuit design method considering the known limitations of the CNTFET manufacturing process is receiving increasing attention. SRAM is a major element constituting microprocessor and is regularly and repeatedly positioned in the cache memory; so, it has the advantage that CNTs can be more easily and densely deposited in SRAM than other circuit blocks. In order to take these advantages, this paper presents a circuit design method for SRAM cells considering CNT density and then evaluates its performance improvement using HSPICE simulation. As a result of simulation, it is found that when CNTFET is applied to SRAM, the gate width can be reduced by about 1.7 times and the read speed also can be improved by about 2 times when the CNT density was increased in the same gate width.