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YoungGun Pu,Jun-Gi Jo,Changsik Yoo,Dojin Park,Seong-Eon Park,Suk-Joong Lee,Kang-Yoon Lee 대한전자공학회 2008 ITC-CSCC :International Technical Conference on Ci Vol.2008 No.7
This paper presents a low power CMOS frequency synthesizer for GPS application that can support multiple reference clocks. The frequency synthesizer has fractional-N phase locked loop structure with sigma-delta modulator to allow multiple reference clock frequencies. The measured phase noise is -126㏈c/㎐ at 1㎒ offset from the carrier. This chip is fabricated with 0.18㎛ CMOS technology, and the die area of the frequency synthesizer is 1.1㎜ × 1.05㎜. The power consumption is 18㎽ at 1.8V supply voltage.
PU, YoungGun,LEE, Kang-Yoon The Institute of Electronics, Information and Comm 2009 IEICE transactions on electronics Vol.92 No.12
<P>This paper presents a wide tuning range VCO with an automatic frequency, gain, and two-step amplitude calibration loop for Digital TV (DTV) tuner applications. To cover the wide tuning range, the fully digital automatic frequency calibration (AFC) loop is used. In addition to the AFC loop, a two-step negative-G<SUB>m</SUB> tuning loop is proposed to provide the optimum negative-G<SUB>m</SUB> to the LC tank in a wide frequency range with a fine resolution. In the coarse negative-G<SUB>m</SUB> tuning loop, the number of active negative-G<SUB>m</SUB> cells is selected digitally based on the target frequency. In the fine negative-G<SUB>m</SUB> tuning loop, the negative-G<SUB>m</SUB> is tuned finely with the bias voltage of the VCO. Also, the digital VCO gain calibration scheme is proposed to compensate for the gain variation in a wide tuning range. The VCO tuning range is 2.6GHz, from 1.7GHz to 4.3GHz, and the power consumption is 2mA to 4mA from a 1.8V supply. The measured VCO phase noise is -120dBc/Hz at 1MHz offset.</P>
Low-Power, All Digital Phase-Locked Loop with a Wide-Range, High Resolution TDC
YoungGun Pu,AnSoo Park,Joon-Sung Park,이강윤 한국전자통신연구원 2011 ETRI Journal Vol.33 No.3
In this paper, we propose a low-power all-digital phase-locked loop (ADPLL) with a wide input range and a high resolution time-to-digital converter (TDC). The resolution of the proposed TDC is improved by using a phase-interpolator and the time amplifier. The phase noise of the proposed ADPLL is improved by using a fine resolution digitally controlled oscillator (DCO) with an active inductor. In order to control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. The die area of the ADPLL is 0.8 mm2 using 0.13 μm CMOS technology. The frequency resolution of the TDC is 1 ps. The DCO tuning range is 58% at 2.4 GHz and the effective DCO frequency resolution is 0.14 kHz. The phase noise of the ADPLL output at 2.4 GHz is –120.5 dBc/Hz with a 1 MHz offset. The total power consumption of the ADPLL is 12 mW from a 1.2 V supply voltage.
Wide-Band Fine-Resolution DCO with an Active Inductor and Three-Step Coarse Tuning Loop
YoungGun Pu,AnSoo Park,Joon-Sung Park,Yeon-Kug Moon,김석기,이강윤 한국전자통신연구원 2011 ETRI Journal Vol.33 No.2
This paper presents a wide-band fine-resolution digitally controlled oscillator (DCO) with an active inductor using an automatic three-step coarse and gain tuning loop. To control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. To cover the wide tuning range, a three-step coarse tuning scheme is used. In addition, the DCO gain needs to be calibrated digitally to compensate for gain variations. The DCO tuning range is 58% at 2.4 GHz, and the power consumption is 6.6 mW from a 1.2 V supply voltage. An effective frequency resolution is 0.14 kHz. The phase noise of the DCO output at 2.4 GHz is –120.67 dBc/Hz at 1 MHz offset.
능동 인덕터를 이용한 광대역 디지털 제어 발진기의 설계
부영건(YoungGun Pu),박안수(AnSoo Park),박형구(HyungGu Park),박준성(Joon-Sung Park),이강윤(Kang-Yoon Lee) 大韓電子工學會 2011 電子工學會論文誌-SD (Semiconductor and devices) Vol.48 No.3
본 논문은 넓은 튜닝 범위와 정밀한 해상도 성능을 가지는 능동 인덕터를 이용한 디지털 제어 발진기에 대한 논문이다. 디지털 제어 발진기의 주파수를 조정하기 위해 능동 인덕터의 트랜스컨덕턴스를 디지털적으로 조정하는 구조를 제안하였으며, 디지털 제어 발진기의 이득 또한 디지털적으로 조정하여 이득 변화를 상쇄하도록 하였다. 또한, 넓은 튜닝 영역과 정밀한 해상도를 구현하기 위해 자동 3 단계 주파수 및 이득 튜닝 루프를 제안하였다. 디지털 제어 발진기의 총 주파수 튜닝 영역은 2.1㎓~3.5㎓로 1.4㎓의 영역으로 이는 2.4㎓의 중간 주파수에 대하여 58 %에 해당한다. 유효 주파수 해상도는 시그마 델타 모듈레이터를 사용하여 0.14 ㎑/LSB를 구현하였다. 제안하는 디지털 제어 발진기는 0.13 ㎛ CMOS 공정으로 설계 되었다. 전체 전력 소모는 1.2 V 공급전압에서 6.6 ㎽이며 위상 잡음 성능은 2.4 ㎓ 중간 주파수의 경우, 1 ㎒ 오프셋에서 -120.67 ㏈c/㎐ 성능을 보이고 있다. This paper presents a wide tuning range, fine-resolution DCO (Digitally Controlled Oscillator) with an active inductor. In order to control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. In addition, the DCO gain needs to be calibrated digitally to compensate for gain variations. To cover the wide tuning range, an automatic three-step coarse tuning scheme is proposed. The DCO total frequency tuning range is 1.4 ㎓ (2.1 ㎓ to 3.5 ㎓), it is 58 % at 2.4 ㎓. An effective frequency resolution is 0.14 ㎑/LSB. The proposed DCO is implemented in 0.13 μm CMOS process. The total power consumption is 6.6 ㎽ from a 1.2 V supply voltage. The phase noise of the DCO output at 2.4 ㎓ is -120.67 ㏈c/Hz at 1 ㎒ offset.
넓은 동적 영역의 파워 검출기를 이용한 DVB-S2용 디지털 자동 이득 제어 시스템
부영건(YoungGun Pu),박준성(Joon-Sung Park),허정(Jeong Hur),이강윤(Kang-Yoon Lee) 大韓電子工學會 2009 電子工學會論文誌-SD (Semiconductor and devices) Vol.46 No.9
본 논문에서는 높은 대역폭과 넓은 동적 영역을 갖는 DVB-S2를 위한 새로운 디지털 이득 제어 시스템을 제안하였다. DVB-S2 시스템의 PAPR은 매우 크며, 요구되는 정착 시간은 매우 작기 때문에 일반적인 폐-루프 아날로그 이득 제어 방식은 사용할 수 없다. 정확한 이득 제어와 기저 대역 모뎀과의 직접적인 인터페이스를 위해서 디지털 이득 제어가 필요하다. 또한 아날로그 이득 제어 방식에 비해 정착 시간과 공정, 전압, 온도 값의 변화에 둔감한 이점을 갖는다. 본 논문에서는 세밀한 해상도와 넓은 이득 영역을 갖기 위해서 AGC 시스템 및 구성회로를 제안하였다. 이 시스템은 높은 대역폭의 디지털 VGA와 넓은 파워 범위를 가진 RMS 검출기, 저 전력의 SAR 타입 ADC, 그리고 디지털 이득 제어기로 구성되어 있다. 파워 소모와 칩 면적을 줄이기 위해 한 개의 SAR 타입 ADC를 사용했으며, ADC 입력은 4개의 파워 검출기를 사용하여 시간 축 상에서 인터리빙 방식으로 구현하였다. 모의실험 및 측정 결과는 제안하는 AGC 시스템의 이득 에러가 10 ㎲ 내에서, 0.25 ㏈보다 낮은 것을 보여주고 있다. 전체 칩은 0.18 ㎛ CMOS 공정을 사용하여 설계하였다. 제안된 IF AGC 시스템의 측정 결과는 0.25 ㏈의 해상도와 80 ㏈의 이득 범위, 8 nV/√㎐의 입력 기준 잡음, IIP₃는 5 ㏈m, 전력 소모는 60 mW임을 보여주고 있다. 파워 검출기는 100 ㎒ 입력에서 35 ㏈의 동적 영역을 갖는다. This paper presents a fully digital gain control system with a new high bandwidth and wide dynamic range power detector for DVB-S2 application. Because the peak-to-average power ratio (PAPR) of DVB-S2 system is so high and the settling time requirement is so stringent, the conventional closed-loop analog gain control scheme cannot be used. The digital gain control is necessary for the robust gain control and the direct digital interface with the baseband modem. Also, it has several advantages over the analog gain control in terms of the settling time and insensitivity to the process, voltage and temperature variation. In order to have a wide gain range with fine step resolution, a new AGC system is proposed. The system is composed of high-bandwidth digital VGAs, wide dynamic range power detectors with RMS detector, low power SAR type ADC, and a digital gain controller. To reduce the power consumption and chip area, only one SAR type ADC is used, and its input is time-interleaved based on four power detectors. Simulation and measurement results show that the new AGC system converges with gain error less than 0.25 ㏈ to the desired level within 10 ㎲. It is implemented in a 0.18 ㎛ CMOS process. The measurement results of the proposed IF AGC system exhibit 80-㏈ gain range with 0.25-㏈ resolution, 8 nV/√㎐ input referred noise, and 5-㏈m IIP₃ at 60-㎽ power consumption. The power detector shows the 35㏈ dynamic range for 100 ㎒ input.
A 350 ㎼ 3.2 ㎓ VCO with an Automatic Amplitude Control Loop in 0.13 ㎛ CMOS process
SangWoo Kim,JoonSung Park,YoungGun Pu,YooSam Na,Kang-Yoon Lee 대한전자공학회 2009 ITC-CSCC :International Technical Conference on Ci Vol.2009 No.7
This paper presents a low-power VCO with an automatic amplitude control loop to compensate for the process, voltage and temperature variation. The settling time of the loop is less than 300 ㎱ in the SS corner case. Adaptive body-biasing (ABB) technique is also used to minimize the power consumption by lowering the threshold voltage of transistors in the negative-Gm core. The power consumption is 350 ㎼ and the phase noise at the 1 ㎒ offset is -117 ㏈c/㎐ when the VCO frequency is 3.2 ㎓.