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고성능 마이크로프로세서 선형주소 생성기 Architecture에 관한 연구
이용석 연세대학교 산업기술연구소 1994 논문집 Vol.26 No.2
This paper describes a linear address generation unit for the superscalar YS6 microprocessor. The superscalar YS6 microprocessor with A-pipe and B-pipe can execute 2 instructions per clock. The linear address generation unit consists of a segmentation unit and a SDCache unit. The segmentation unit and the SDCache unit of YS6 microprocessor speed up the linear address generation process by using the following techniques. The segmentation unit can generate two linear addresses per clock by using multiport register files and 4-input adders and support two concurrent stack operations per clock. It takes 9 clocks to execute a macroinstruction, 'Mov Sreg, reg', in previous architectures. However, YS6 processor with SDCache unit executes this instruction in 2 clocks. The SDCache unit solves cache consistency problem with main memory by using the Subset protocol. This unit is described with Verilog HDL (Hardware Description Language) and its functional operation is verified.
이종근,지용석,정희석 한국스포츠리서치 2003 한국 스포츠 리서치 Vol.20 No.1
The purpose of this study is to examine the job satisfaction of the job characteristics of golf instructors and to investigate the important factors affected by that. To achieve this purpose, 300 leaders who are certified semi-pro among golf leaders throughout the country are selected as the population, but the questionnaires from 274 subjects are adopted for the data of the final analysis. And this thesis attempts to use the way of Correlation Analysis and Covariance Structure Analysis using LISREL, as a statistical method to verify an established hypothesis. The results have processed through the analysis are summarized as follows. First, the determinative variables, such as the challenge for job, the suitableness for job, the security for work, the utility expected for job and the variables satisfying expectation have had a positive influence on the occupational commitment of golf instructors, but job challenge, amount of duty, and the need for achievement have had a negative effect on that. Second, the determinative variables, such as job suitableness, job security and expected utility, and the variables satisfying expectation have had a positive influence on the occupational contentment, but job challenge, amount of duty, and the need for achievement have not affected on that. On the other hand, the control variable which is their marital status also has been exercised a positive influence on the job satisfaction.
An On-chip Multiprocessor Miroprocessor with Shared MMU and Cache
Lee, Yong-Hwan,Jeong, Woo-Kyeong,An, Sang-Jun,Lee, Yong-Surk The Korean Institute of Electrical Engineers 1997 Journal of Electrical Engineering and Information Vol.2 No.4
A multiprocessor microprocessor named SMPC(scaleable multiprocessor chip) that contains tow IU (integer unit) is presented in this paper. It can execute multiple instructions from several tasks exploiting task-level parallelism that is free from instruction dependencies, and provide high performance and throughput on both single program and multiprogramming environments. the IU is a 32-bit scalar processor expecially designed to boost up the performance of string manipulations which are frequently used in RDBMS(relational data base management system) applications. A memory management unit and a data cache shared by two IUs improve the performance and reduce the chip area required. ETH SMPC is implemented in VLSI circuit by custom design and automated design tools.
An On-chip Multiprocessor Microprocessor with Shared MMU and Cache
Yong-Hwan Lee,Woo-Kyeong Jeong,Sang-Jun An,Yong-Surk Lee 한국정보과학회 1997 Journal of Electrical Engineering and Information Vol.2 No.4
A multiprocessor microprocessor named SMPC(scaleable multiprocessor chip) that contains two IU (integer unit) is presented in this paper. It can execute multiple instructions from several tasks exploiting task-level parallelism that is free from instruction dependencies, and provide high performance and throughput on both single program and multiprogramming environments. The IU is a 32-bit scalar processor especially designed to boost up the performance of string manipulations which are frequently used in RDBMS(relational data base management system) applications. A memory management unit and a data cache shared by two IUs improve the performance and reduce the chip area required. The SMPC is implemented in VLSI circuit by custom design and automated design tools.
Yong-joo Lee,Sang-hoon Kim,Jae-hee Sim,Yong-surk Lee 대한전자공학회 2007 ITC-CSCC :International Technical Conference on Ci Vol.2007 No.7
In this paper we propose a new RFID (Radio Frequency Identification) active tag anti-collision algorithm which is fully compatible with an ISO-IEC_CD 18000-6C generation 2 standard for passive tags. We optimized and improved a conventional anti-collision algorithm in the ISO-IEC_CD 18000-6C standard to minimize the hardware overhead and maintain compatibility with conventional interrogators. Using a new sub-slot algorithm, we reduced the probability of collision. As a result of simulation, the time needed to read multiple tags is reduced by about 48% with the proposed sub-slot algorithm compared to the original algorithm exemplified in the ISO-IEC_CD 18000- 6C standard.
An On-chip Multiprocessor microprocessor with Shared MMU and Cache
Lee, Yong-hwan,Jeong, Woo-kyeong,Lee, Yong-surk THE RESEARCH INSTITUTE OF ASIC DESIGN YONSEI UNIVE 1997 Journal of the Research Institute of ASIC Design Vol.4 No.1
A multiprocessor microprocessor named SMPC (scaleable multiprocessor chip) that contains two IU(integer unit) is presented in this paper. It can execute multiple instructions from several tasks exploiting task-level parallelism that is free from intstruction dependencies, and provide high performance and throughput on both single program and multiprogramming environment. The IU is a 32-bit scalar processor especially designed to boost up the performance of string manipulations which are frequently used in RDBMS(relational data base management system) applications. A memory management unit and a data cache shared by two IUs improve the performance and reduce the chip area required. The SMPC is implemented in VLSI circuit by custom design and automated design tools.