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Toshikazu Sekine,Nobuyuki Ichimura,Yasuhiro Takahashi,Kunikatsu Kobayashi 대한전자공학회 2007 ITC-CSCC :International Technical Conference on Ci Vol.2007 No.7
A simple wave absorber with specified reflection and transmission coefficients at both sides is proposed. This wave absorber consists of two transparent dielectric layers with three transparent resistance films. This wave absorber is transparent and electromagnetic waves are absorbed in both sides. Then it is suitable for the indoor use as electromagnetic wave separater.
A 4-bit Multiplier Using a Two Phase Drive Adiabatic Dynamic CMOS Logic
Yasuhiro Takahashi,Toshikazu Sekine,Michio Yokoyama 대한전자공학회 2007 ITC-CSCC :International Technical Conference on Ci Vol.2007 No.7
This paper describe the design and VLSI implementation of a multiplier using an adiabatic logic which is called a two phase drive adiabatic dynamic CMOS logic (2PADCL) circuit. Circuit operation and performance has been evaluated using a 4×4-bit 2PADCL multiplier fabricated in a 1.2 ㎛ CMOS process. The experimental results show that the multiplier was operated with clock frequencies 800㎑. The total power dissipation of the 4×4-bit 2PADCL multiplier was also 5.19 ㎽ at the 1.5 VDC power supply voltage.
Daiki Ichikawa,Toshikazu Sekine,Yasuhiro Takahashi,Kunikatsu Kobayashi 대한전자공학회 2007 ITC-CSCC :International Technical Conference on Ci Vol.2007 No.7
A simple modeling method in the time domain for interconnect with frequency dependent loss is presented. This model consists of nonuniform transmission line with frequency independent per unit length parameters. Then time domain characteristics can be efficiently calculated.
An estimation method for 2-port S-parameters using 4-port connection circuit with leakage couplings
Shinji Ohno,Toshikazu Sekine,Yasuhiro Takahashi 대한전자공학회 2015 ITC-CSCC :International Technical Conference on Ci Vol.2015 No.6
An estimation method for S-parameters of 2-port circuit by using connection circuits with leakage couplings is presented. In our method, two ports of 4- port connection circuit are terminated with unknown 2- port circuit or known loads. And the S-parameters between remaining two ports are measured. Advantages of our method is that the S-parameters of 2-port circuit are to be estimated only by solving the linear least squares problem. Our method can be applied to determine the S-parameters of the circuit with a difficult port to connect the probe of the instrument as the IC package and to determine the S-parameters of the circuit ground is not common.
Two Phase Clocked Adiabatic Static CMOS Logic and its Logic Family
Anuar, Nazrul,Takahashi, Yasuhiro,Sekine, Toshikazu The Institute of Electronics and Information Engin 2010 Journal of semiconductor technology and science Vol.10 No.1
This paper proposes a two-phase clocked adiabatic static CMOS logic (2PASCL) circuit that utilizes the principles of adiabatic switching and energy recovery. The low-power 2PASCL circuit uses two complementary split-level sinusoidal power supply clocks whose height is equal to $V_{dd}$. It can be directly derived from static CMOS circuits. By removing the diode from the charging path, higher output amplitude is achieved and the power consumption of the diode is eliminated. 2PASCL has switching activity that is lower than dynamic logic. We also design and simulate NOT, NAND, NOR, and XOR logic gates on the basis of the 2PASCL topology. From the simulation results, we find that 2PASCL 4-inverter chain logic can save up to 79% of dissipated energy as compared to that with a static CMOS logic at transition frequencies of 1 to 100 MHz. The results indicate that 2PASCL technology can be advantageously applied to low power digital devices operated at low frequencies, such as radio-frequency identifications (RFIDs), smart cards, and sensors.
Adiabatic Logic versus CMOS for Low Power Applications
Nazrul Anuar,Yasuhiro Takahashi,Toshikazu Sekine 대한전자공학회 2009 ITC-CSCC :International Technical Conference on Ci Vol.2009 No.7
This paper presents a new quasi adiabatic logic family that uses a pair of complementary split-level sinusoidal power supply clocks for digital low power applications such as sensors. The proposed two phase clocked adiabatic static CMOS logic (2PASCL) circuit utilizes the principle of adiabatic switching and energy recovery. By removing the diode at the charging path, higher output amplitude is achieved and the power consumption of the diode is eliminated. We design and simulate NOT, NAND, NOR and Exclusive-OR logic gates based on 2PASCL with SPICE implemented using 0.18 ㎛ CMOS technology. A driving pulse with the height equal to Vdd is supplied to the gates. From the simulation results, 2PASCL inverter logic can save up to 97% of energy dissipation compared with static CMOS logic at transition frequencies of 10 to 100 ㎒. It also shows the lowest in energy dissipation compared with other proposed simple adiabatic logic inverters.