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Tourism in retrospect of COVID-19 on global perspective using analytical hierarchy process
Saha Jayanta,Haldar Subrata,Bhattacharya Subhasis,Paul Suman 대한공간정보학회 2021 Spatial Information Research Vol.29 No.6
Covid-19 pandemic has brought remarkable shocks over tourism globally. In case of tourism such experience of epidemic is quite new in terms of time gestation. Even world agencies cannot estimate the amount of loss and fails to predict the full pace running stage of the sector. The study tries to estimate the impact of pandemic over the tourism. Rather than these, the main aspect of the study is to formulate a rank resulted by tourism impact of the studied countries over its economics considering the variables like GDP share of tourism and number of tourist arrivals (2017, 2018 and 2019), tourism dependency rate, tourism competitive index, jobs directly depends on tourism and contribution of tourism in terms of international receipts. The study uses Analytical Hierarchical Process to estimate the impact of Covid-19 over tourism. Results shows the countries with higher dependencies over tourism severely affected and those results are in linearity.
Pujarini Ghosh,Subhasis Haldar,R. S. Gupta,Mridula Gupta 대한전자공학회 2012 Journal of semiconductor technology and science Vol.12 No.4
An intrinsic small signal equivalent circuit model of Cylindrical/Surrounded gate MOSFET is proposed. Admittance parameters of the device are extracted from circuit analysis and intrinsic circuit elements are presented in terms of real and imaginary parts of the admittance parameters. S parameters are then evaluated and justified with the simulated data extracted from 3D device simulation.
Pujarini Ghosh,Subhasis Haldar,R. S. Gupta,Mridula Gupta 대한전자공학회 2012 Journal of semiconductor technology and science Vol.12 No.4
A Dual metal gate stack cylindrical/surrounded gate MOSFET (DMGSA CGT/SGT MOSFET) has been proposed and an analytical model has been developed to examine the impact of this structure in suppressing short channel effects and in enhancing the device performance. It is demonstrated that incorporation of gate stack along with dual metal gate architecture results in improvement in short channel immunity. It is also examined that for DMGSA CGT/SGT the minimum surface potential in the channel reduces, resulting increase in electron velocity and thereby improving the carrier transport efficiency. Furthermore, the device has been analyzed at different bias point for both single material gate stack architecture (SMGSA) and dual material gate stack architecture (DMGSA) and found that DMGSA has superior characteristics as compared to SMGSA devices. The analytical results obtained from the proposed model agree well with the simulated results obtained from 3D ATLAS Device simulator.
Ghosh, Pujarini,Haldar, Subhasis,Gupta, R.S.,Gupta, Mridula The Institute of Electronics and Information Engin 2012 Journal of semiconductor technology and science Vol.12 No.4
A Dual metal gate stack cylindrical/ surrounded gate MOSFET (DMGSA CGT/SGT MOSFET) has been proposed and an analytical model has been developed to examine the impact of this structure in suppressing short channel effects and in enhancing the device performance. It is demonstrated that incorporation of gate stack along with dual metal gate architecture results in improvement in short channel immunity. It is also examined that for DMGSA CGT/SGT the minimum surface potential in the channel reduces, resulting increase in electron velocity and thereby improving the carrier transport efficiency. Furthermore, the device has been analyzed at different bias point for both single material gate stack architecture (SMGSA) and dual material gate stack architecture (DMGSA) and found that DMGSA has superior characteristics as compared to SMGSA devices. The analytical results obtained from the proposed model agree well with the simulated results obtained from 3D ATLAS Device simulator.
Ghosh, Pujarini,Haldar, Subhasis,Gupta, R.S.,Gupta, Mridula The Institute of Electronics and Information Engin 2012 Journal of semiconductor technology and science Vol.12 No.4
An intrinsic small signal equivalent circuit model of Cylindrical/Surrounded gate MOSFET is proposed. Admittance parameters of the device are extracted from circuit analysis and intrinsic circuit elements are presented in terms of real and imaginary parts of the admittance parameters. S parameters are then evaluated and justified with the simulated data extracted from 3D device simulation.
Paul Suman,Bhattacharya Subhasis,Mandal Buddhadev,Haldar Subrata,Mandal Somnath,Kundu Sanjit,Biswas Anupam 대한공간정보학회 2021 Spatial Information Research Vol.29 No.3
SARS-CoV-2 has been transmitted and outbreak took place in India during the last week before nationwide 1st lockdown took place. Urban areas found more vulnerable and reported nearly 65% of cases during every phase of lockdown. Mumbai, among four metropolitan cities found huge number of containment zones with nearly 30% of SARS-CoV-2 cases indicating clustering of cases. Most of the containment zones of SARS-CoV-2 cases in Kolkata Municipal Corporation found a significant relation with slum areas. The study primarily tries considering the nature of SARS-CoV-2 cases in different urban centres with the help of cartographic techniques. AHP method has been used to determine the factors responsible for such concentration of SARS-CoV-2 cases with vulnerability assessment (exposure, sensitivity and resilience) and risks. Before nationwide lockdown starts, the share of urban centres found 25% which has been transformed into nearly 60% at the end of 3rd phase of lockdown. Growth rate of SARS-CoV-2 cases found very high for Chennai and Thane with less number of doubling time to nation. Slum concentration and containment density shows a higher degree of correlation in Kolkata Municipal Corporation. Risk map also shows the concentration of cases in central and north Kolkata with higher degree of diseases exposure and sensitivity. Control measures must be taken by the central and state Government to minimise the transmission rate of SARS-CoV-2 mainly urban areas. As urban area contributing a higher share of SARS-CoV-2 cases, a proper management plan must be enforce.
Mangla, Tina,Sehgal, Amit,Saxena, Manoj,Haldar, Subhasis,Gupta, Mridula,Gupta, R.S. The Institute of Electronics and Information Engin 2005 Journal of semiconductor technology and science Vol.5 No.3
Quantization effects (QEs), which manifests when the device dimensions are comparable to the de Brogile wavelength, are becoming common physical phenomena in the present micro-/nanometer technology era. While most novel devices take advantage of QEs to achieve fast switching speed, miniature size and extremely small power consumption, the mainstream CMOS devices (with the exception of EEPROMs) are generally suffering in performance from these effects. In this paper, an analytical model accounting for the QEs and poly-depletion effects (PDEs) at the silicon (Si)/dielectric interface describing the capacitance-voltage (C-V) and current-voltage (I-V) characteristics of MOS devices with thin oxides is developed. It is also applicable to multi-layer gate-stack structures, since a general procedure is used for calculating the quantum inversion charge density. Using this inversion charge density, device characteristics are obtained. Also solutions for C-V can be quickly obtained without computational burden of solving over a physical grid. We conclude with comparison of the results obtained with our model and those obtained by self-consistent solution of the $Schr{\ddot{o}}dinger$ and Poisson equations and simulations reported previously in the literature. A good agreement was observed between them.
Tina Mangla,Amit Sehgal,Manoj Saxena,Subhasis Haldar,Mridula Gupta,R. S. Gupta 대한전자공학회 2005 Journal of semiconductor technology and science Vol.5 No.3
Quantization effects (QEs), which manifests when the device dimensions are comparable to the de Brogile wavelength, are becoming common physical phenomena in the present micro-/nanometer technology era. While most novel devices take advantage of QEs to achieve fast switching speed, miniature size and extremely small power consumption, the mainstream CMOS devices (with the exception of EEPROMs) are generally suffering in performance from these effects. In this paper, an analytical model accounting for the QEs and polydepletion effects (PDEs) at the silicon (Si)/dielectric interface describing the capacitance-voltage (C-V) and current-voltage (I-V) characteristics of MOS devices with thin oxides is developed. It is also applicable to multi-layer gate-stack structures, since a general procedure is used for calculating the quantum inversion charge density. Using this inversion charge density, device characteristics are obtained. Also solutions for C-V can be quickly obtained without computational burden of solving over a physical grid. We conclude with comparison of the results obtained with our model and those obtained by selfconsistent solution of the Schrodinger and Poisson equations and simulations reported previously in the literature. A good agreement was observed between them.
Optimization of Gate Stack MOSFETs with Quantization Effects
Mangla, Tina,Sehgal, Amit,Saxena, Manoj,Haldar, Subhasis,Gupta, Mridula,Gupta, R.S. The Institute of Electronics and Information Engin 2004 Journal of semiconductor technology and science Vol.4 No.3
In this paper, an analytical model accounting for the quantum effects in MOSFETs has been developed to study the behaviour of $high-{\kappa}$ dielectrics and to calculate the threshold voltage of the device considering two dielectrics gate stack. The effect of variation in gate stack thickness and permittivity on surface potential, inversion layer charge density, threshold voltage, and $I_D-V_D$ characteristics have also been studied. This work aims at presenting a relation between the physical gate dielectric thickness, dielectric constant and substrate doping concentration to achieve targeted threshold voltage, together with minimizing the effect of gate tunneling current. The results so obtained are compared with the available simulated data and the other models available in the literature and show good agreement.
Optimization of Gate Stack MOSFETs with Quantization Effects
Tina Mangla,Amit Sehgal,Manoj Saxena,Subhasis Haldar,Mridula Gupta,R.S.Gupta 대한전자공학회 2004 Journal of semiconductor technology and science Vol.4 No.3
In this paper, an analytical model accounting for the quantum effect. in MOSFETs has been developed to study the behaviour of high-k dielectric. and to calculate the threshold voltage of the device considering two dielectrics gate stack. The effect of variation in gate stack thickness and permittivity on surface potential, inversion layer charge density, threshold voltage, and In-Vo characteristics have also been studied. This work aims at presenting a relation between the physical gate dielectric thickness, dielectric constant and substrate doping concentration to achie"e targeted threshold voltage, together with minimizing the effect of gate tunneling current. The results so obtained are compared with the available simulated data and the other models available in the literature and show good agreement.<br/> Index Terms-Quantization effects (QEs), Triangular Potential Well (TPW), Gate stack, Equivalent oxide thickness (EOT)<br/>