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Rhee, Woo-Geun,Ainspan, Herschel,Friedman, Daniel J.,Rasmus, Todd,Garvin, Stacy,Cranford, Clay The Institute of Electronics and Information Engin 2008 Journal of semiconductor technology and science Vol.8 No.3
This paper describes bandwidth linearization techniques in phase-locked loop (PLL) design for common-clock serial link applications. Utilizing a continuously tunable single-input dual-path LC VCO and a constant-gain phase detector, a proposed architecture is well suited to implementing PLLs that must be compliant with standards that specify minimum and maximum allowable bandwidths such as PCI Express Gen2 or FB-DIMM applications. A prototype 4.75 to 6.1-GHz PLL is implemented in 90-nm CMOS. Measurement results show that the PLL bandwidth and random jitter (RJ) variations are well regulated and that the use of a differentially controlled dual-path VCO is important for deterministic jitter (DJ) performance.
Woogeun Rhee,Herschel Ainspan,Daniel J. Friedman,Todd Rasmus,Stacy Garvin,Clay Cranford 대한전자공학회 2008 Journal of semiconductor technology and science Vol.8 No.3
This paper describes bandwidth linearization techniques in phase-locked loop (PLL) design for common-clock serial link applications. Utilizing a continuously tunable single-input dual-path LC VCO and a constant-gain phase detector, a proposed architecture is well suited to implementing PLLs that must be compliant with standards that specify minimum and maximum allowable bandwidths such as PCI Express Gen2 or FB-DIMM applications. A prototype 4.75 to 6.1-㎓ PLL is implemented in 90-nm CMOS. Measurement results show that the PLL bandwidth and random jitter (RJ) variations are well regulated and that the use of a differentially controlled dualpath VCO is important for deterministic jitter (DJ) performance.