http://chineseinput.net/에서 pinyin(병음)방식으로 중국어를 변환할 수 있습니다.
변환된 중국어를 복사하여 사용하시면 됩니다.
High Performance and FPGA Implementation of Scalable Video Encoder
Park, Seongmo,Kim, Hyunmi,Byun, Kyungjin The Institute of Electronics and Information Engin 2014 IEIE Transactions on Smart Processing & Computing Vol.3 No.6
This paper, presents an efficient hardware architecture of high performance SVC(Scalable Video Coding). This platform uses dedicated hardware architecture to improve its performance. The architecture was prototyped in Verilog HDL and synthesized using the Synopsys Design Compiler with a 65nm standard cell library. At a clock frequency of 266MHz, This platform contains 2,500,000 logic gates and 750,000 memory gates. The performance of the platform is indicated by 30 frames/s of the SVC encoder Full HD($1920{\times}1080$), HD($1280{\times}720$), and D1($720{\times}480$) at 266MHz.
Efficient hardware implementation and analysis of true random-number generator based on beta source
Park, Seongmo,Choi, Byoung Gun,Kang, Taewook,Park, Kyunghwan,Kwon, Youngsu,Kim, Jongbum Electronics and Telecommunications Research Instit 2020 ETRI Journal Vol.42 No.4
This paper presents an efficient hardware random-number generator based on a beta source. The proposed generator counts the values of "0" and "1" and provides a method to distinguish between pseudo-random and true random numbers by comparing them using simple cumulative operations. The random-number generator produces labeled data indicating whether the count value is a pseudo- or true random number according to its bit value based on the generated labeling data. The proposed method is verified using a system based on Verilog RTL coding and LabVIEW for hardware implementation. The generated random numbers were tested according to the NIST SP 800-22 and SP 800-90B standards, and they satisfied the test items specified in the standard. Furthermore, the hardware is efficient and can be used for security, artificial intelligence, and Internet of Things applications in real time.
A lightweight true random number generator using beta radiation for IoT applications
Park, Kyunghwan,Park, Seongmo,Choi, Byoung Gun,Kang, Taewook,Kim, Jongbum,Kim, Young-Hee,Jin, Hong-Zhou Electronics and Telecommunications Research Instit 2020 ETRI Journal Vol.42 No.6
This paper presents a lightweight true random number generator (TRNG) using beta radiation that is useful for Internet of Things (IoT) security. In general, a random number generator (RNG) is required for all secure communication devices because random numbers are needed to generate encryption keys. Most RNGs are computer algorithms and use physical noise as their seed. However, it is difficult to obtain physical noise in small IoT devices. Since IoT security functions are required in almost all countries, IoT devices must be equipped with security algorithms that can pass the cryptographic module validation programs of each country. In this regard, it is very cumbersome to embed security algorithms, random number generation algorithms, and even physical noise sources in small IoT devices. Therefore, this paper introduces a lightweight TRNG comprising a thin-film beta-radiation source and integrated circuits (ICs). Although the ICs are currently being designed, the IC design was functionally verified at the board level. Our random numbers are output from a verification board and tested according to National Institute of Standards and Technology standards.
A Low Power Design of H.264 Codec Based on Hardware and Software Co-design
Seongmo Park(박성모),Sukho Lee(이석호),KyoungSeon Shin(신경선),Jae-Jin Lee(이재진),Moo-Kyoung Chung(정무경),Jun-Young Lee(이준영),Nak-Woong Eum(엄낙웅) 한국통신학회 2008 정보와 통신 Vol.25 No.12
In this paper, we present a low-power design of H.264 codec based on dedicated hardware and software solution on EMP(ETRI Multi-Core Platform). The dedicated hardware scheme has reducing computation using motion estimation skip and reducing memory access for motion estimation. The design reduces data transfer load to 66% compared to conventional method. The gate count of H.264 encoder and the performance is about 455k and 43Mhz@30fps with D1(720×480) for H.264 encoder. The software solution is with ASIP(Application Specific Instruction Processor) that it is SIMD(Single Instruction Multiple Data), Dual Issue VLIW(Very Long Instruction Word) core, specified register file for SIMD, internal memory and data memory access for memory controller, 6 step pipeline, and 32 bits bus width. Performance and gate count is 400㎒@30fps with CIF(Common Intermediated Format) and about 100k per core for H.264 decoder.