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A Low-Power ECC Check Bit Generator Implementation in DRAMs
Sang-Uhn Cha,Yun-Sang Lee,Hongil Yoon 대한전자공학회 2006 Journal of semiconductor technology and science Vol.6 No.4
A low-power ECC check bit generator is presented with competent DRAM implementation with minimal speed loss, area overhead and power consumption. The ECC used in the proposed scheme is a variant form of the minimum weight column code. The spatial and temporal correlations of input data are analyzed and the input paths of the check bit generator are ordered for the on-line adaptable power savings up to 24.4% in the benchmarked cases. The chip size overhead is estimated to be under 0.3% for a 80㎚ 1Gb DRAM implementation.
A Low-Power ECC Check Bit Generator Implementation in DRAMs
Cha, Sang-Uhn,Lee, Yun-Sang,Yoon, Hong-Il The Institute of Electronics and Information Engin 2006 Journal of semiconductor technology and science Vol.6 No.4
A low-power ECC check bit generator is presented with competent DRAM implementation with minimal speed loss, area overhead and power consumption. The ECC used in the proposed scheme is a variant form of the minimum weight column code. The spatial and temporal correlations of input data are analyzed and the input paths of the check bit generator are ordered for the on-line adaptable power savings up to 24.4% in the benchmarked cases. The chip size overhead is estimated to be under 0.3% for a 80nm 1Gb DRAM implementation.