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RISS 인기검색어
- 검색키워드
- 저자 : Nazrul Anuar (검색결과 3 건)
- 무료
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Two Phase Clocked Adiabatic Static CMOS Logic and its Logic Family
Anuar, Nazrul,Takahashi, Yasuhiro,Sekine, Toshikazu The Institute of Electronics and Information Engin 2010 Journal of semiconductor technology and science Vol.10 No.1
This paper proposes a two-phase clocked adiabatic static CMOS logic (2PASCL) circuit that utilizes the principles of adiabatic switching and energy recovery. The low-power 2PASCL circuit uses two complementary split-level sinusoidal power supply clocks whose height is equal to $V_{dd}$. It can be directly derived from static CMOS circuits. By removing the diode from the charging path, higher output amplitude is achieved and the power consumption of the diode is eliminated. 2PASCL has switching activity that is lower than dynamic logic. We also design and simulate NOT, NAND, NOR, and XOR logic gates on the basis of the 2PASCL topology. From the simulation results, we find that 2PASCL 4-inverter chain logic can save up to 79% of dissipated energy as compared to that with a static CMOS logic at transition frequencies of 1 to 100 MHz. The results indicate that 2PASCL technology can be advantageously applied to low power digital devices operated at low frequencies, such as radio-frequency identifications (RFIDs), smart cards, and sensors.
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Adiabatic Logic versus CMOS for Low Power Applications
Nazrul Anuar,Yasuhiro Takahashi,Toshikazu Sekine 대한전자공학회 2009 ITC-CSCC :International Technical Conference on Ci Vol.2009 No.7
This paper presents a new quasi adiabatic logic family that uses a pair of complementary split-level sinusoidal power supply clocks for digital low power applications such as sensors. The proposed two phase clocked adiabatic static CMOS logic (2PASCL) circuit utilizes the principle of adiabatic switching and energy recovery. By removing the diode at the charging path, higher output amplitude is achieved and the power consumption of the diode is eliminated. We design and simulate NOT, NAND, NOR and Exclusive-OR logic gates based on 2PASCL with SPICE implemented using 0.18 ㎛ CMOS technology. A driving pulse with the height equal to Vdd is supplied to the gates. From the simulation results, 2PASCL inverter logic can save up to 97% of energy dissipation compared with static CMOS logic at transition frequencies of 10 to 100 ㎒. It also shows the lowest in energy dissipation compared with other proposed simple adiabatic logic inverters.
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Two Phase Clocked Adiabatic Static CMOS Logic and its Logic Family
Nazrul Anuar,Yasuhiro Takahashi,Toshikazu Sekine 대한전자공학회 2010 Journal of semiconductor technology and science Vol.10 No.1
This paper proposes a two-phase clocked adiabatic static CMOS logic (2PASCL) circuit that utilizes the principles of adiabatic switching and energy recovery. The low-power 2PASCL circuit uses two complementary split-level sinusoidal power supply clocks whose height is equal to Vdd. It can be directly derived from static CMOS circuits. By removing the diode from the charging path, higher output amplitude is achieved and the power consumption of the diode is eliminated. 2PASCL has switching activity that is lower than dynamic logic. We also design and simulate NOT, NAND, NOR, and XOR logic gates on the basis of the 2PASCL topology. From the simulation results, we find that 2PASCL 4-inverter chain logic can save up to 79% of dissipated energy as compared to that with a static CMOS logic at transition frequencies of 1 to 100 ㎒. The results indicate that 2PASCL technology can be advantageously applied to low power digital devices operated at low frequencies, such as radio-frequency identifications (RFIDs), smart cards, and sensors.
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