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A Minimum-Complexity 0.35㎛ Surface-Channel CMOS Process for Digital Logic and Analog Applications
Demirlioglu, E.,Yoon, E.,Pierce, J.,Blair, C.,Moverly, L.,Geha, S.,Wei, J.,Ciari, R.,Chen, K.,Kuo, C. S.,Sadjadi, R.,Brown, K.,Sethna, P.,Bariya, A.,Rocchetta, S. Della 대한전자공학회 1993 ICVC : International Conference on VLSI and CAD Vol.3 No.1
This paper presents a minimum-complexity 0.35 ㎛ CMOS technology with high performance and law mask count. Scaled LOCOS isolation and implantation through the field oxide allow a simplified process flow and provide adequate isolation at minimum active pacing. This architecture produces a retrograde well structure without requiring a MeV-energy implant. Surface channel PMOS and NMOS transistors with double diffused drains and silicide give high drive currents of 0.23 and 0.47mA/㎛, respectively, and low off-state leakage below 10pA/㎛ at drain voltage of 3.3 V.