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Generalized Isomorphism between Synchronous Circuits and State Machines
Shunji Nishimura,Motoki Amagasaki,Toshinori Sueyoshi 대한전자공학회 2015 ITC-CSCC :International Technical Conference on Ci Vol.2015 No.6
This paper proposes a new model which describes a circuit and its behavior by adopting a category theory. In this model, we define a new class of synchronous elements “comprehensive latches”, and show that for any such comprehensive latch synchronous circuit, there is a state machine that behaves similarly to the circuit. That kind of isomorphism is well-known only for D-FlipFlop synchronous circuit, and our isomorphism is its generalization since comprehensive latches include D-FlipFlops. The key idea of our isomorphism is that a state machine is synchronized by a natural transformation (categorical term) in an analogous way of that circuit is synchronized by a synchronous element. D-Latches are also elements of our comprehensive latches, and thus, for a given D-Latch synchronous circuit, the isomorphism provides a state machine correspond to the circuit.
Low-cost Hardware that Accelerates Frequent Item Counting with an FPGA
Mpho Gift Doctor Gololo,Hendarmawan,Qian Zhao,Motoki Amagasaki,Masahiro Iida,Morihiro Kuga,Toshinori Sueyoshi 대한전자공학회 2017 IEIE Transactions on Smart Processing & Computing Vol.6 No.5
In this paper, hardware acceleration using a field programmable gate array is proposed to provide low development–cost and high-performance stream processing hardware. This research is proposed as an enhancement to the software-based application for frequent item counting (FIC) and to contribute to hardware-based FIC for hardware/software co-design. We design an experiment by taking advantage of high-level synthesis (HLS) and the heterogeneous Computing Oriented Development Environment (hCODE), an open source platform providing a methodology and a tool for scalable and portable Internet Protocol design. The proposed scheme considers optimization techniques offered by HLS compilers, such as the pipeline technique, loop unrolling, and memory partition. Our implementation shows that the proposed scheme achieves a better overall performance than a software scheme, and more importantly, introduces fast and low development costs for hardware accelerators.