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Ko, Kyul,Son, Dokyun,Woo, Changbeom,Kang, Myounggon,Shin, Hyungcheol American Scientific Publishers 2017 Journal of Nanoscience and Nanotechnology Vol.17 No.10
<P>In this work, the work function variation (WFV) and process variation effect (PVE) on 5 nm node gate-all-around (GAA) silicon 3D stacked nanowire field-effect transistor (NWFET) devices are studied through technology computer-aided design (TCAD) simulations. The WFV effect on 3D stacked NWFETs leads to stronger immunity compared to the same effect on single NWFETs. On the other hand, the 3D stacked NWFET is significantly affected when each stack is varied due to PVE. As the PVE becomes increasingly more serious, it is important to analyze the degree of variability of each stack in a NWFET. In addition, we closely investigate the WFV effect and device an accurate guideline with regard to the NW diameters of single and 3D stacked NWFETs affected by the PVE.</P>
Ko, Kyul,Woo, Changbeom,Kim, Minsoo,Seo, Youngsoo,Kim, Shinkeun,Kang, Myounggon,Shin, Hyungcheol The Institute of Electronics and Information Engin 2017 Journal of semiconductor technology and science Vol.17 No.5
In this paper, intrinsic characteristics of gate-all-around (GAA) nanoplate (NP) vertical FET (VFET) were investigated for single and multi-channel structure through 3-D technology computer-aided design (TCAD) simulations. The vertical device has strong immunity for the unprecedented short channel effects (SCE) and intrinsic gate delay compared with the lateral device owing to the flexible expansion channel in vertical direction. The proposed single and multi-channel NP VFETs (NP height = 40 nm) exhibit excellent characteristics with $I_{on}/I_{off}$ > $10^5$, subthreshold swing (SS) < 73 mV/decade, and drain-induced barrier lowering (DIBL) < 60 mV/V.
Kyul Ko,Changbeom Woo,Minsoo Kim,Youngsoo Seo,Shinkeun Kim,Myounggon Kang,Hyungcheol Shin 대한전자공학회 2017 Journal of semiconductor technology and science Vol.17 No.5
In this paper, intrinsic characteristics of gate-all-around (GAA) nanoplate (NP) vertical FET (VFET) were investigated for single and multichannel structure through 3-D technology computeraided design (TCAD) simulations. The vertical device has strong immunity for the unprecedented short channel effects (SCE) and intrinsic gate delay compared with the lateral device owing to the flexible expansion channel in vertical direction. The proposed single and multi-channel NP VFETs (NP height = 40 nm) exhibit excellent characteristics with Ion/Ioff > 105, subthreshold swing (SS) < 73 mV/decade, and draininduced barrier lowering (DIBL) < 60 mV/V.
Ko, Kyul,Son, Dokyun,Kang, Myounggon,Shin, Hyungcheol Elsevier 2018 Solid-state electronics Vol.140 No.-
<P><B>Abstract</B></P> <P>In this work, work-function variation (WFV) on 5 nm node gate-all-around (GAA) silicon 3D stacked nanowire FET (NWFET) and FinFET devices are studied for 6-T SRAM cells through 3D technology computer-aided design (TCAD) simulation. The NWFET devices have strong immunity for the unprecedented short channel effects (SCEs) compared with the FinFET devices owing to increased gate controllability. However, due to the narrow gate area, the single NWFET is more vulnerable to WFV effects than FinFET devices. Our results show that the WFV effects on single NWFETs are larger than the FinFETs by 45–55%. In the case of standard SRAM bit cells (high density: 111 bit cell), the variation of read stability (read static noise margin) on single NWFETs are larger than the FinFETs by 65–75%. Therefore, to improve the performance and having immunity to WFV effects, it is important to analyze the degree of variability in 3D stacked device architectures without area penalty. Moreover, we investigated the WFV effects for an accurate guideline with regard to grain size (GS) and channel area of 3D stacked NWFET in 6-T SRAM bit cells.</P>
Analysis and Comparison of Interface Trap for Single and 3D Stacked Nanowire FET
Ko, Kyul,Son, Dokyun,Kang, Myounggon,Shin, Hyungcheol American Scientific Publishers 2017 Journal of Nanoscience and Nanotechnology Vol.17 No.10
<P>In this work, we investigate the interface trap (IFT) variation effect, one of the most important reliability issues, in 5-nm node gate-all-around (GAA) single and 3D stacked nanowire field-effect transistors (NWFETs). Comparing the IFT variation effect, the 3D stacked NWFET was found to have stronger immunity compared to a single NWFET. However, the 3D stacked NWFET is significantly affected by the variation of each stack due to the process variation effect (PVE). For this reason, the goals of this paper were to reach a comprehensive understanding of the IFT variation effect and to provide an accurate guideline pertaining to the NW diameters in single NWFETs and 3D stacked NWFETs.</P>
MOSFET에서 트랩의 전계와 SRH 전류 변화에 따른 TAT GIDL 전류 변화 분석 및 검증
고결(Kyul Ko),유성원(Sung-Won Yoo),고형우(Hyungwoo Ko),신형철(Hyungcheol Shin) 대한전자공학회 2015 대한전자공학회 학술대회 Vol.2015 No.11
We have observed TAT GIDL current variation induced by the electric field between two traps and the variation of SRH current at trap-detrap site in MOSFET. Unlike the previous research, the direction of electric field without generation-recombination site dose not have a right angle so that the sum of electric field becomes a different value. Additionally, the variation of SRH current is not simply obtained by the distance between two traps. The variation includes the factor of electric field instead. As a result, the leakage current, which is the product of two variables, can be induced by a different method.
실리콘 내부에 있는 slow trap에 의한 TAT 전류 변화 분석
고결(Kyul Ko),유성원(Sung-Won Yoo),이현슬(Hyunseul Lee),서영수(Youngsoo Seo),전상빈(Sangbin Jeon),고형우(Hyungwoo Ko),전현옥(Jeon-Hyun Ok),신형철(Hyungcheol Shin) 대한전자공학회 2015 대한전자공학회 학술대회 Vol.2015 No.6
In this paper, we present an analysis of the trap-assisted tunneling (TAT) area on gate-induced drain leakage (GIDL) current variation by the slow trap in silicon using an analytical equations. And, TAT current variation is compared with the type of charge carrier. Finally, we compared TAT GIDL current variation by slow trap in oxide with silicon region depending on the perpendicular distance of the slow trap from the interface and temperature.