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실폐광폐수의 중금속 제거를 위한 AFMR 공정 운전 연구
백병천,김광복 國立 麗水大學校 環境問題硏究所 2000 環境硏究論文集 Vol.3 No.-
This research is to establish operation technology of AFMR(Anaerobic Floating Media Reactor) Process for heavy metals removal from raw acid mine drainage. Two AFMR were operated at hydraulic retention time(HRT) of 3days, COD/sulfate ratio of 0.5, temperature of 30℃, and alkalinity from 600㎎/ℓ to 1,000㎎/ℓ (as CaCO_(3)). AT COD/sulfate(SO_(4)^(2-)) ratio of 0.5 and temperature of 30℃, the maximum ratio of reduced sulfate(SO_(4)^(2-))/removed COD(㎎/㎎) kept about 1.34 and the reactor achieved 99.9% of Cr, Cu and Fe, 99.4% of Pb, 99% of Zn, 98% of Cd, and 92.5% of Mn removal efficiencies, respectively. Increment of alkalinity in influent can lead to reduce level of heavy metals in effluent . In order to achieve the efficient removal of heavy metal from raw acid mine drainage, alkalinity of range from 800㎎/ℓ to 1,000㎎/ℓ (as CaCO_(3)) has to be supplied to the influent feed, Sulfate reducing bacteria(SRB) of rods and bacillus types were also observed on surface floating media used in this study.
홍경용,남철현,최상복,위광복,김기열 韓國保健敎育.健康增進學會 2001 보건교육건강증진학회지 Vol.18 No.3
This study was conducted to examine middle and high school students' knowledge level of first aid, health promotion, and safety. Data were collected from 1.165 students from March 6, 2000 to April 4, 2000. The results of this study are summarized as follows. 1.80.1% of the respondents felt the necessity of first aid. The sources of information about methods of first arid were school (43.9%), mass media (15.6%), and self-study (10.5%). 30.0% of them never leaned the methods of first aid. 2.In the case of obtaining information on first aid through mass media, 58.2% of them got it from TV. 7.3% of them obtained it from magazines, while 5.8% of them got it from newspapers. According to their viewpoints of adequate time to teach the methods of first aid, 38.6% of them thought that the methods had to be taught in the primary school and 25.2% of them thought that they had to be taught in the kindergarten. 24.9% of them replied that the methods had to be taught in the middle school, while 11.3% of them replied that they had to be taught in the high school. 3.The points for knowledge of first aid were 98.29±20.91 on the basis of 150 points (65.5 points on the basis of 100 points). The points showed significant differences in the variables of sex, education level, numbers of siblings, parents' education level, and guardian's occupation.
New Two-Level L1 Data Cache Bypassing Technique for High Performance GPUs
( Gwang Bok Kim ),( Cheol Hong Kim ) 한국정보처리학회 2021 Journal of information processing systems Vol.17 No.1
On-chip caches of graphics processing units (GPUs) have contributed to improved GPU performance by reducing long memory access latency. However, cache efficiency remains low despite the facts that recent GPUs have considerably mitigated the bottleneck problem of L1 data cache. Although the cache miss rate is a reasonable metric for cache efficiency, it is not necessarily proportional to GPU performance. In this study, we introduce a second key determinant to overcome the problem of predicting the performance gains from L1 data cache based on the assumption that miss rate only is not accurate. The proposed technique estimates the benefits of the cache by measuring the balance between cache efficiency and throughput. The throughput of the cache is predicted based on the warp occupancy information in the warp pool. Then, the warp occupancy is used for a second bypass phase when workloads show an ambiguous miss rate. In our proposed architecture, the L1 data cache is turned off for a long period when the warp occupancy is not high. Our two-level bypassing technique can be applied to recent GPU models and improves the performance by 6% on average compared to the architecture without bypassing. Moreover, it outperforms the conventional bottleneck-based bypassing techniques.
저전력 1차 명령어 캐쉬를 위한 명령어 흐름 기반 이른 웨이 결정 기법
김광복(Gwang Bok Kim),김종면(Jong Myon Kim),김철홍(Cheol Hong Kim) 한국컴퓨터정보학회 2016 韓國컴퓨터情報學會論文誌 Vol.21 No.9
Recent embedded processors employ set-associative L1 instruction cache to improve the performance. The energy consumption in the set-associative L1 instruction cache accounts for considerable portion in the embedded processor. When an instruction is required from the processor, all ways in the set-associative instruction cache are accessed in parallel. In this paper, we propose the technique to reduce the energy consumption in the set-associative L1 instruction cache effectively by accessing only one way. Gshare branch predictor is employed to predict the instruction flow and determine the way to fetch the instruction. When the branch prediction is untaken, next instruction in a sequential order can be fetched from the instruction cache by accessing only one way. According to our simulations with SPEC2006 benchmarks, the proposed technique requires negligible hardware overhead and shows 20% energy reduction on average in 4-way L1 instruction cache.
김광복(Gwang Bok Kim),허신(Shin Heu) 한국정보과학회 2010 한국정보과학회 학술발표논문집 Vol.37 No.1C
BPMS, ERP, SCM 등 프로세스 인식 정보시스템들이 널리 쓰이게 되면서 프로세스 마이닝에 대한 연구가 활발하게 이루어지고 있다. 프로세스 마이닝은 프로세스가 실행되는 동안 저장된 이벤트 로그로부터 정보를 추출하는 기법이다. 추출된 로그정보는 비즈니스 프로세스의 분석 및 재설계에 사용될 프로세스 모델을 생성하게 된다. 프로세스 마이닝 기법은 프로세스의 자동화 및 기업의 업무정보들을 관리하는 프로세스 기반 정보시스템의 정확성 및 효율성을 위한 중요한 부분을 차지하지만 현재까지의 연구는 생성된 이벤트 로그로부터 프로세스 모델을 재설계하는 프로세스 발견 기법 (Process Discovery Technique)을 적용한 부분에서만 활발히 진행되었다. 프로세스 마이닝은 프로세스 발견 기법 외에도 프로세스 적합성검사 기법 (Process Conformance Checking Technique) 및 프로세스 확장 기법 (Process Extension Technique)이 존재한다. 이들은 많은 프로세스 발견 기법에 대한 연구들이 진행되고 나서야 최근 프로세스 마이닝의 이슈로 떠오르고 있다. 본 논문에서는 프로세스 적합성 검사를 위해 수집된 이벤트 로그와 기존에 나와 있는 여러 가지 프로세스 발견 알고리즘을 통해 생성된 프로세스를 수치적으로 비교할 수 있는 두 가지 애트리뷰트를 제시하였다.
GPU 성능 향상을 위한 지연시간 숨김 기반 워프 스케줄링
김광복(Gwang Bok Kim),김종면(Jong Myon Kim),김철홍(Cheol Hong Kim) 한국컴퓨터정보학회 2019 韓國컴퓨터情報學會論文誌 Vol.24 No.4
LRR(Loose Round Robin) warp scheduling policy for GPU architecture results in high warp-level parallelism and balanced loads across multiple warps. However, traditional LRR policy makes multiple warps execute long latency operations at the same time. In cases that no more warps to be issued under long latency, the throughput of GPUs may be degraded significantly. In this paper, we propose a new warp scheduling policy which utilizes latency hiding, leading to more utilized memory resources in high performance GPUs. The proposed warp scheduler prioritizes memory instruction based on GTO(Greedy Then Oldest) policy in order to provide reduced memory stalls. When no warps can execute memory instruction any more, the warp scheduler selects a warp for computation instruction by round robin manner. Furthermore, our proposed technique achieves high performance by using additional information about recently committed warps. According to our experimental results, our proposed technique improves GPU performance by 12.7% and 5.6% over LRR and GTO on average, respectively.