An Efficient BIRA Utilizing Characteristics of Spare Pivot Faults

Cho, Keewon,Lee, Young-Woo,Seo, Sungyoul,Kang, Sungho IEEE 2019 IEEE transactions on computer-aided design of inte Vol.38 No.3

<P>The current growth of micro-semiconductor technologies requires that an effective solution be found to address the yield and reliability issues associated with embedded memories. A common solution is built-in redundancy analysis (BIRA), which is utilized to guarantee reasonable memory yields. The most common form of BIRA is a module that stores and analyzes fault addresses with a 2-D spare architecture. When the performance of BIRA is evaluated, numerous different parameters are considered, such as repair rate, area overhead, and analysis speed. Because there is a tradeoff between these criteria, many BIRA approaches have been studied so that an ideal BIRA can be found. A novel BIRA approach that focuses on a 100% repair rate and a minimal area overhead is proposed in this paper. In the fault collection phase, the proposed BIRA stores only the essential part of fault addresses in content addressable memories (CAMs), with the rest of the fault addresses being stored in spare memories. After the fault collection phase, a redundancy analysis procedure is performed with the minimum amount of fault information that is stored in the proposed CAM structure. By doing so, the proposed BIRA algorithm can repair all repairable faulty memories while maintaining a minimal area overhead. Our experimental results confirm that the proposed approach exhibits outstanding performance for area overhead, especially when compared to other BIRA approaches that have 100% repair rates.</P>

A Survey of Repair Analysis Algorithms for Memories

Cho, Keewon,Kang, Wooheon,Cho, Hyungjun,Lee, Changwook,Kang, Sungho Association for Computing Machinery 2016 ACM computing surveys Vol.49 No.3

<P>Current rapid advancements in deep submicron technologies have enabled the implementation of very large memory devices and embedded memories. However, the memory growth increases the number of defects, reducing the yield and reliability of such devices. Faulty cells are commonly repaired by using redundant cells, which are embedded in memory arrays by adding spare rows and columns. The repair process requires an efficient redundancy analysis (RA) algorithm. Spare architectures for the repair of faulty memory include one-dimensional (1D) spare architectures, two-dimensional (2D) spare architectures, and configurable spare architectures. Of these types, 2D spare architectures, which prepare extra rows and columns for repair, are popular because of their better repairing efficiency than 1D spare architectures and easier implementation than configurable spare architectures. However, because the complexity of the RA is NP-complete, the RA algorithm should consider various factors in order to determine a repair solution. The performance depends on three factors: analysis time, repair rate, and area overhead. In this article, we survey RA algorithms for memory devices as well as built-in repair algorithms for improving these performance factors. Built-in redundancy analysis techniques for emergent three-dimensional integrated circuits are also discussed. Based on this analysis, we then discuss future research challenges for faulty-memory repair studies.</P>

Submicron-Sized MRAM Array with Local Field Switching Architecture

Keewon Kim,Injun Hwang,Tae-Wan Kim,Ji Young Bae,Young Jin Cho,Kwang-Seok Kim,Sung Hoon Choa 한국자기학회 2007 한국자기학회 학술연구발표회 논문개요집 Vol.- No.-

Intraoperative Neurophysiological Monitoring : A Review of Techniques Used for Brain Tumor Surgery in Children

Kim, Keewon,Cho, Charles,Bang, Moon-suk,Shin, Hyung-ik,Phi, Ji-Hoon,Kim, Seung-Ki The Korean Neurosurgical Society 2018 Journal of Korean neurosurgical society Vol.61 No.3

Intraoperative monitoring (IOM) utilizes electrophysiological techniques as a surrogate test and evaluation of nervous function while a patient is under general anesthesia. They are increasingly used for procedures, both surgical and endovascular, to avoid injury during an operation, examine neurological tissue to guide the surgery, or to test electrophysiological function to allow for more complete resection or corrections. The application of IOM during pediatric brain tumor resections encompasses a unique set of technical issues. First, obtaining stable and reliable responses in children of different ages requires detailed understanding of normal age-adjusted brain-spine development. Neurophysiology, anatomy, and anthropometry of children are different from those of adults. Second, monitoring of the brain may include risk to eloquent functions and cranial nerve functions that are difficult with the usual neurophysiological techniques. Third, interpretation of signal change requires unique sets of normative values specific for children of that age. Fourth, tumor resection involves multiple considerations including defining tumor type, size, location, pathophysiology that might require maximal removal of lesion or minimal intervention. IOM techniques can be divided into monitoring and mapping. Mapping involves identification of specific neural structures to avoid or minimize injury. Monitoring is continuous acquisition of neural signals to determine the integrity of the full longitudinal path of the neural system of interest. Motor evoked potentials and somatosensory evoked potentials are representative methodologies for monitoring. Free-running electromyography is also used to monitor irritation or damage to the motor nerves in the lower motor neuron level : cranial nerves, roots, and peripheral nerves. For the surgery of infratentorial tumors, in addition to free-running electromyography of the bulbar muscles, brainstem auditory evoked potentials or corticobulbar motor evoked potentials could be combined to prevent injury of the cranial nerves or nucleus. IOM for cerebral tumors can adopt direct cortical stimulation or direct subcortical stimulation to map the corticospinal pathways in the vicinity of lesion. IOM is a diagnostic as well as interventional tool for neurosurgery. To prove clinical evidence of it is not simple. Randomized controlled prospective studies may not be possible due to ethical reasons. However, prospective longitudinal studies confirming prognostic value of IOM are available. Furthermore, oncological outcome has also been shown to be superior in some brain tumors, with IOM. New methodologies of IOM are being developed and clinically applied. This review establishes a composite view of techniques used today, noting differences between adult and pediatric monitoring.

Low Cost Endurance Test-pattern Generation for Multi-level Cell Flash Memory

Cha, Jaewon,Cho, Keewon,Yu, Seunggeon,Kang, Sungho The Institute of Electronics and Information Engin 2017 Journal of semiconductor technology and science Vol.17 No.1

A new endurance test-pattern generation on NAND-flash memory is proposed to improve test cost. We mainly focus on the correlation between the data-pattern and the device error-rate during endurance testing. The novelty is the development of testing method using quasi-random pattern based on device architectures in order to increase the test efficiency during time-consuming endurance testing. It has been proven by the experiments using the commercial 32 nm NAND flash-memory. Using the proposed method, the error-rate increases up to 18.6% compared to that of the conventional method which uses pseudo-random pattern. Endurance testing time using the proposed quasi-random pattern is faster than that of using the conventional pseudo-random pattern since it is possible to reach the target error rate quickly using the proposed one. Accordingly, the proposed method provides more low-cost testing solutions compared to the previous pseudo-random testing patterns.

Low Cost Endurance Test-pattern Generation for Multi-level Cell Flash Memory

Jaewon Cha,Keewon Cho,Seunggeon Yu,Sungho Kang 대한전자공학회 2017 Journal of semiconductor technology and science Vol.17 No.1

A new endurance test-pattern generation on NAND-flash memory is proposed to improve test cost. We mainly focus on the correlation between the data-pattern and the device error-rate during endurance testing. The novelty is the development of testing method using quasi-random pattern based on device architectures in order to increase the test efficiency during time-consuming endurance testing. It has been proven by the experiments using the commercial 32 nm NAND flash-memory. Using the proposed method, the error-rate increases up to 18.6% compared to that of the conventional method which uses pseudo-random pattern. Endurance testing time using the proposed quasi-random pattern is faster than that of using the conventional pseudorandom pattern since it is possible to reach the target error rate quickly using the proposed one. Accordingly, the proposed method provides more lowcost testing solutions compared to the previous pseudo-random testing patterns.

A Statistic-Based Scan Chain Reordering for Energy-Quality Scalable Scan Test

Seo, Sungyoul,Cho, Keewon,Lee, Young-Woo,Kang, Sungho IEEE 2018 IEEE journal on emerging and selected topics in ci Vol.8 No.3

<P>As a rapid progress in technology processes, the design integration of high-performance system-on-chip (SoC) is on the rise rapidly. To incorporate hundreds of IP cores into a single chip, a modern SoC exceeds ten million gates with a large number of scan cells, so that it leads excessive energy consumption. In this paper, we present an energy-quality (EQ) scalable scan test method using new scan chain reordering. The method conducts three stages, which are a new scan partitioning, a scan partition-based X-filling, and a statistic-based scan stitching to reduce test energy consumption without quality degradation. The proposed scan partitioning method prevents excessive routing overhead. Then, the proposed scan chain reordering is performed by a statistical analysis considering EQ scalability. It also covers two frequently-used fault models: 1) stuck-at and 2) transition delay. The experimental results show that the proposed scan chain reordering method achieved lower energy consumption and relieve the routing overhead on ISCAS’89, ITC’99, and IWLS’05 OpenCores benchmark circuits in most cases compared with previously existing methods without excessive runtime overhead.</P>

BRANCH 단일 분석기의 ROS 최적화 방안

이우성(Woosung Lee),조기원(Keewon Cho),김주영(Jooyoung Kim),강성호(Sungho Kang) 한국통신학회 2015 한국통신학회 학술대회논문집 Vol.2015 No.1

Hardware-Efficient Built-In Redundancy Analysis for Memory With Various Spares

Kim, Jooyoung,Lee, Woosung,Cho, Keewon,Kang, Sungho IEEE 2017 IEEE transactions on very large scale integration Vol.25 No.3

<P>Memory capacity continues to increase, and many semiconductor manufacturing companies are trying to stack memory dice for larger memory capacities. Therefore, built-in redundancy analysis (BIRA) is of utmost importance because the probability of fault occurrence increases with a larger memory capacity. A traditional spare structure that consists of simple rows and columns is somewhat inadequate for multiple memory blocks BIRA because the hardware overhead and spare allocation efficiency are degraded. The proposed BIRA uses various types of spares and can achieve a higher yield than a simple row and column spare structure. Herein, we propose a BIRA that can achieve an optimal repair rate using various spare types. The proposed analyzer can exhaustively search not only row and column spare types but also global and local spare types. In addition, this paper proposes a fault-storing content-addressable memory (CAM) structure. The proposed CAM is small and collects faults efficiently. The experimental results show a high repair rate with a small hardware overhead and a short analysis time.</P>

Overcoming the Challenges in the Development and Implementation of Artificial Intelligence in Radiology: A Comprehensive Review of Solutions Beyond Supervised Learning

Hong Gil-Sun,Jang Miso,Kyung Sunggu,Cho Kyungjin,Jeong Jiheon,Lee Grace Yoojin,Shin Keewon,Kim Ki Duk,Ryu Seung Min,Seo Joon Beom,Lee Sang Min,Kim Namkug 대한영상의학회 2023 Korean Journal of Radiology Vol.24 No.11

Artificial intelligence (AI) in radiology is a rapidly developing field with several prospective clinical studies demonstrating its benefits in clinical practice. In 2022, the Korean Society of Radiology held a forum to discuss the challenges and drawbacks in AI development and implementation. Various barriers hinder the successful application and widespread adoption of AI in radiology, such as limited annotated data, data privacy and security, data heterogeneity, imbalanced data, model interpretability, overfitting, and integration with clinical workflows. In this review, some of the various possible solutions to these challenges are presented and discussed; these include training with longitudinal and multimodal datasets, dense training with multitask learning and multimodal learning, self-supervised contrastive learning, various image modifications and syntheses using generative models, explainable AI, causal learning, federated learning with large data models, and digital twins.